| Macpaul Lin | 024db0a | 2011-09-23 17:31:27 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Andes Technology Corporation |
| 3 | * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 18 | */ |
| 19 | |
| 20 | #ifndef __AG102_H |
| 21 | #define __AG102_H |
| 22 | |
| 23 | /* |
| 24 | * Hardware register bases |
| 25 | */ |
| 26 | |
| 27 | /* PCI Controller */ |
| 28 | #define CONFIG_FTPCI100_BASE 0x90000000 |
| 29 | /* LPC Controller */ |
| 30 | #define CONFIG_LPC_IO_BASE 0x90100000 |
| 31 | /* LPC Controller */ |
| 32 | #define CONFIG_LPC_BASE 0x90200000 |
| 33 | |
| 34 | /* NDS32 Data Local Memory 01 */ |
| 35 | #define CONFIG_NDS_DLM1_BASE 0x90300000 |
| 36 | /* NDS32 Data Local Memory 02 */ |
| 37 | #define CONFIG_NDS_DLM2_BASE 0x90400000 |
| 38 | |
| 39 | /* Synopsys DWC DDR2/1 Controller */ |
| 40 | #define CONFIG_DWCDDR21MCTL_BASE 0x90500000 |
| 41 | /* DMA Controller */ |
| 42 | #define CONFIG_FTDMAC020_BASE 0x90600000 |
| 43 | /* FTIDE020_S IDE (ATA) Controller */ |
| 44 | #define CONFIG_FTIDE020S_BASE 0x90700000 |
| 45 | /* USB OTG Controller */ |
| 46 | #define CONFIG_FZOTG266HD0A_BASE 0x90800000 |
| 47 | /* Andes L2 Cache Controller */ |
| 48 | #define CONFIG_NCEL2C100_BASE 0x90900000 |
| 49 | /* XGI XG22 GPU */ |
| 50 | #define CONFIG_XGI_XG22_BASE 0x90A00000 |
| 51 | /* GMAC Ethernet Controller */ |
| 52 | #define CONFIG_FTGMAC100_BASE 0x90B00000 |
| 53 | /* AHB Controller */ |
| 54 | #define CONFIG_FTAHBC020S_BASE 0x90C00000 |
| 55 | /* AHB-to-APB Bridge Controller */ |
| 56 | #define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000 |
| 57 | /* External AHB2AHB Controller */ |
| 58 | #define CONFIG_EXT_AHB2AHB_BASE 0x90E00000 |
| 59 | /* Andes Multi-core Interrupt Controller */ |
| 60 | #define CONFIG_NCEMIC100_BASE 0x90F00000 |
| 61 | |
| 62 | /* |
| 63 | * APB Device definitions |
| 64 | */ |
| 65 | /* Compat Flash Controller */ |
| 66 | #define CONFIG_FTCFC010_BASE 0x94000000 |
| 67 | /* APB - SSP (SPI) (without AC97) Controller */ |
| 68 | #define CONFIG_FTSSP010_01_BASE 0x94100000 |
| 69 | /* UART1 - APB STUART Controller (UART0 in Linux) */ |
| 70 | #define CONFIG_FTUART010_01_BASE 0x94200000 |
| 71 | /* FTSDC010 SD Controller */ |
| 72 | #define CONFIG_FTSDC010_BASE 0x94400000 |
| 73 | /* APB - SSP with HDA/AC97 Controller */ |
| 74 | #define CONFIG_FTSSP010_02_BASE 0x94500000 |
| 75 | /* UART2 - APB STUART Controller (UART1 in Linux) */ |
| 76 | #define CONFIG_FTUART010_02_BASE 0x94600000 |
| 77 | /* PCU Controller */ |
| 78 | #define CONFIG_ANDES_PCU_BASE 0x94800000 |
| 79 | /* FTTMR010 Timer */ |
| 80 | #define CONFIG_FTTMR010_BASE 0x94900000 |
| 81 | /* Watch Dog Controller */ |
| 82 | #define CONFIG_FTWDT010_BASE 0x94A00000 |
| 83 | /* FTRTC010 Real Time Clock */ |
| 84 | #define CONFIG_FTRTC010_BASE 0x98B00000 |
| 85 | /* GPIO Controller */ |
| 86 | #define CONFIG_FTGPIO010_BASE 0x94C00000 |
| 87 | /* I2C Controller */ |
| 88 | #define CONFIG_FTIIC010_BASE 0x94E00000 |
| 89 | /* PWM - Pulse Width Modulator Controller */ |
| 90 | #define CONFIG_FTPWM010_BASE 0x94F00000 |
| 91 | |
| 92 | /* Debug LED */ |
| 93 | #define CONFIG_DEBUG_LED 0x902FFFFC |
| 94 | /* Power Management Unit */ |
| 95 | #define CONFIG_FTPMU010_BASE 0x98100000 |
| 96 | |
| 97 | #endif /* __AG102_H */ |