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git01.mediatek.com / filogic / uboot / 6732dcf18267f35b6166fd73dadbb2c48d123611 / . / arch / arm / dts / imx8mm-venice-gw7905.dtsi
blob: 9646eb9e4928436ee0d0e80cbb9e8ac237ed8131 [file] [log] [blame]
Tim Harvey586599b2023-08-15 15:01:14 -0700[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2023 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/leds/common.h>
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9
10/ {
11 led-controller {
12 compatible = "gpio-leds";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpio_leds>;
15
16 led-0 {
17 function = LED_FUNCTION_STATUS;
18 color = <LED_COLOR_ID_GREEN>;
19 gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
20 default-state = "on";
21 linux,default-trigger = "heartbeat";
22 };
23
24 led-1 {
25 function = LED_FUNCTION_STATUS;
26 color = <LED_COLOR_ID_RED>;
27 gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
28 default-state = "off";
29 };
30 };
31
32 pcie0_refclk: pcie0-refclk {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <100000000>;
36 };
37
38 pps {
39 compatible = "pps-gpio";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_pps>;
42 gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
43 status = "okay";
44 };
45
46 reg_usb2_vbus: regulator-usb2-vbus {
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_reg_usb2_en>;
49 compatible = "regulator-fixed";
50 regulator-name = "usb2_vbus";
51 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
52 enable-active-high;
53 regulator-min-microvolt = <5000000>;
54 regulator-max-microvolt = <5000000>;
55 };
56
57 reg_usdhc2_vmmc: regulator-usdhc2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
60 compatible = "regulator-fixed";
61 regulator-name = "SD2_3P3V";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
64 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
65 enable-active-high;
66 };
67};
68
69/* off-board header */
70&ecspi2 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_spi2>;
73 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
74 status = "okay";
75};
76
77&gpio1 {
78 gpio-line-names =
79 "", "", "", "",
80 "", "", "", "",
81 "", "", "", "",
82 "", "gpioa", "gpiob", "",
83 "", "", "", "",
84 "", "", "", "",
85 "", "", "", "",
86 "", "", "", "";
87};
88
89&gpio4 {
90 gpio-line-names =
91 "", "", "", "pci_usb_sel",
92 "", "", "", "pci_wdis#",
93 "", "", "", "",
94 "", "", "", "",
95 "", "", "", "",
96 "", "", "", "",
97 "", "", "", "",
98 "", "", "", "";
99};
100
101&gpio5 {
102 gpio-line-names =
103 "", "", "", "",
104 "gpioc", "gpiod", "", "",
105 "", "", "", "",
106 "", "", "", "",
107 "", "", "", "",
108 "", "", "", "",
109 "", "", "", "",
110 "", "", "", "";
111};
112
113&i2c2 {
114 clock-frequency = <400000>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_i2c2>;
117 status = "okay";
118
119 eeprom@52 {
120 compatible = "atmel,24c32";
121 reg = <0x52>;
122 pagesize = <32>;
123 };
124};
125
126/* off-board header */
127&i2c3 {
128 clock-frequency = <400000>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_i2c3>;
131 status = "okay";
132};
133
134&pcie_phy {
135 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
136 fsl,clkreq-unsupported;
137 clocks = <&pcie0_refclk>;
138 clock-names = "ref";
139 status = "okay";
140};
141
142&pcie0 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_pcie0>;
145 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
146 status = "okay";
147};
148
149/* GPS */
150&uart1 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_uart1>;
153 status = "okay";
154};
155
156/* USB1 - Type C front panel SINK port J14 */
157&usbotg1 {
158 dr_mode = "peripheral";
159 status = "okay";
160};
161
162/* USB2 4-port USB3.0 HUB:
163 * P1 - USBC connector (host only)
164 * P2 - USB2 test connector
165 * P3 - miniPCIe full card
166 * P4 - miniPCIe half card
167 */
168&usbotg2 {
169 dr_mode = "host";
170 vbus-supply = <&reg_usb2_vbus>;
171 status = "okay";
172};
173
174/* microSD */
175&usdhc2 {
176 pinctrl-names = "default", "state_100mhz", "state_200mhz";
177 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
178 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
179 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
180 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
181 vmmc-supply = <&reg_usdhc2_vmmc>;
182 bus-width = <4>;
183 status = "okay";
184};
185
186&iomuxc {
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_hog>;
189
190 pinctrl_hog: hoggrp {
191 fsl,pins = <
192 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */
193 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */
194 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */
195 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */
196 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */
197 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */
198 >;
199 };
200
201 pinctrl_gpio_leds: gpioledgrp {
202 fsl,pins = <
203 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */
204 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */
205 >;
206 };
207
208 pinctrl_i2c2: i2c2grp {
209 fsl,pins = <
210 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
211 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
212 >;
213 };
214
215 pinctrl_i2c3: i2c3grp {
216 fsl,pins = <
217 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
218 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
219 >;
220 };
221
222 pinctrl_pcie0: pciegrp {
223 fsl,pins = <
224 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106
225 >;
226 };
227
228 pinctrl_pps: ppsgrp {
229 fsl,pins = <
230 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106
231 >;
232 };
233
234 pinctrl_reg_usb2_en: regusb2grp {
235 fsl,pins = <
236 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */
237 >;
238 };
239
240 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
241 fsl,pins = <
242 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
243 >;
244 };
245
246 pinctrl_spi2: spi2grp {
247 fsl,pins = <
248 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140
249 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140
250 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140
251 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140
252 >;
253 };
254
255 pinctrl_uart1: uart1grp {
256 fsl,pins = <
257 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
258 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
259 >;
260 };
261
262 pinctrl_usdhc2: usdhc2grp {
263 fsl,pins = <
264 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
265 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
266 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
267 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
268 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
269 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
270 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
271 >;
272 };
273
274 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
275 fsl,pins = <
276 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
277 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
278 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
279 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
280 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
281 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
282 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
283 >;
284 };
285
286 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
287 fsl,pins = <
288 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
289 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
290 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
291 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
292 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
293 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
294 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
295 >;
296 };
297
298 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
299 fsl,pins = <
300 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
301 >;
302 };
303};