blob: dd8a33f15bea08f4a261109118e85710daca18b1 [file] [log] [blame]
Fabrice Gasnier95c868e2018-04-26 17:00:46 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
5 *
6 * Originally based on the Linux kernel v4.16 drivers/regulator/stm32-vrefbuf.c
7 */
8
Patrick Delaunayde59a1e2020-11-06 19:01:42 +01009#define LOG_CATEGORY UCLASS_REGULATOR
10
Fabrice Gasnier95c868e2018-04-26 17:00:46 +020011#include <clk.h>
12#include <dm.h>
13#include <asm/io.h>
Simon Glass9bc15642020-02-03 07:36:16 -070014#include <dm/device_compat.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060015#include <linux/bitops.h>
Fabrice Gasnier95c868e2018-04-26 17:00:46 +020016#include <linux/iopoll.h>
17#include <linux/kernel.h>
18#include <power/regulator.h>
19
20/* STM32 VREFBUF registers */
21#define STM32_VREFBUF_CSR 0x00
22
23/* STM32 VREFBUF CSR bitfields */
24#define STM32_VRS GENMASK(6, 4)
25#define STM32_VRS_SHIFT 4
26#define STM32_VRR BIT(3)
27#define STM32_HIZ BIT(1)
28#define STM32_ENVR BIT(0)
29
30struct stm32_vrefbuf {
31 void __iomem *base;
32 struct clk clk;
33 struct udevice *vdda_supply;
34};
35
Patrick Delaunay5a10c752019-06-21 15:26:49 +020036static const int stm32_vrefbuf_voltages[] = {
Fabrice Gasnier95c868e2018-04-26 17:00:46 +020037 /* Matches resp. VRS = 000b, 001b, 010b, 011b */
38 2500000, 2048000, 1800000, 1500000,
39};
40
41static int stm32_vrefbuf_set_enable(struct udevice *dev, bool enable)
42{
43 struct stm32_vrefbuf *priv = dev_get_priv(dev);
44 u32 val;
45 int ret;
46
Fabrice Gasnierfec2a902020-06-12 10:40:58 +020047 if (enable && !(readl(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR)) {
48 /*
49 * There maybe an overshoot:
50 * - when disabling, then re-enabling vrefbuf too quickly
51 * - or upon platform reset as external capacitor maybe slow
52 * discharging (VREFBUF is HiZ at reset by default).
53 * So force active discharge (HiZ=0) for 1ms before enabling.
54 */
55 clrbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_HIZ);
56 udelay(1000);
57 }
58
59 clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_ENVR,
60 enable ? STM32_ENVR : 0);
Fabrice Gasnier95c868e2018-04-26 17:00:46 +020061 if (!enable)
62 return 0;
63
64 /*
65 * Vrefbuf startup time depends on external capacitor: wait here for
66 * VRR to be set. That means output has reached expected value.
67 * ~650us sleep should be enough for caps up to 1.5uF. Use 10ms as
68 * arbitrary timeout.
69 */
70 ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val,
71 val & STM32_VRR, 10000);
72 if (ret < 0) {
73 dev_err(dev, "stm32 vrefbuf timed out: %d\n", ret);
74 clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_ENVR,
75 STM32_HIZ);
76 return ret;
77 }
78
79 return 0;
80}
81
82static int stm32_vrefbuf_get_enable(struct udevice *dev)
83{
84 struct stm32_vrefbuf *priv = dev_get_priv(dev);
85
86 return readl(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR;
87}
88
89static int stm32_vrefbuf_set_value(struct udevice *dev, int uV)
90{
91 struct stm32_vrefbuf *priv = dev_get_priv(dev);
92 unsigned int i;
93
94 for (i = 0; i < ARRAY_SIZE(stm32_vrefbuf_voltages); i++) {
95 if (uV == stm32_vrefbuf_voltages[i]) {
96 clrsetbits_le32(priv->base + STM32_VREFBUF_CSR,
97 STM32_VRS, i << STM32_VRS_SHIFT);
98 return 0;
99 }
100 }
101
102 return -EINVAL;
103}
104
105static int stm32_vrefbuf_get_value(struct udevice *dev)
106{
107 struct stm32_vrefbuf *priv = dev_get_priv(dev);
108 u32 val;
109
110 val = readl(priv->base + STM32_VREFBUF_CSR) & STM32_VRS;
111 val >>= STM32_VRS_SHIFT;
112
113 return stm32_vrefbuf_voltages[val];
114}
115
116static const struct dm_regulator_ops stm32_vrefbuf_ops = {
117 .get_value = stm32_vrefbuf_get_value,
118 .set_value = stm32_vrefbuf_set_value,
119 .get_enable = stm32_vrefbuf_get_enable,
120 .set_enable = stm32_vrefbuf_set_enable,
121};
122
123static int stm32_vrefbuf_probe(struct udevice *dev)
124{
125 struct stm32_vrefbuf *priv = dev_get_priv(dev);
126 int ret;
127
128 priv->base = dev_read_addr_ptr(dev);
129
130 ret = clk_get_by_index(dev, 0, &priv->clk);
131 if (ret) {
132 dev_err(dev, "Can't get clock: %d\n", ret);
133 return ret;
134 }
135
136 ret = clk_enable(&priv->clk);
137 if (ret) {
138 dev_err(dev, "Can't enable clock: %d\n", ret);
139 return ret;
140 }
141
142 ret = device_get_supply_regulator(dev, "vdda-supply",
143 &priv->vdda_supply);
144 if (ret) {
145 dev_dbg(dev, "No vdda-supply: %d\n", ret);
146 return 0;
147 }
148
149 ret = regulator_set_enable(priv->vdda_supply, true);
150 if (ret) {
151 dev_err(dev, "Can't enable vdda-supply: %d\n", ret);
152 clk_disable(&priv->clk);
153 }
154
155 return ret;
156}
157
158static const struct udevice_id stm32_vrefbuf_ids[] = {
159 { .compatible = "st,stm32-vrefbuf" },
160 { }
161};
162
163U_BOOT_DRIVER(stm32_vrefbuf) = {
164 .name = "stm32-vrefbuf",
165 .id = UCLASS_REGULATOR,
166 .of_match = stm32_vrefbuf_ids,
167 .probe = stm32_vrefbuf_probe,
168 .ops = &stm32_vrefbuf_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700169 .priv_auto = sizeof(struct stm32_vrefbuf),
Fabrice Gasnier95c868e2018-04-26 17:00:46 +0200170};