Rene Griessl | 979beee | 2014-11-07 16:53:48 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de> |
| 3 | * based on the U-Boot Asix driver as well as information |
| 4 | * from the Linux AX88179_178a driver |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <usb.h> |
| 11 | #include <net.h> |
| 12 | #include <linux/mii.h> |
| 13 | #include "usb_ether.h" |
| 14 | #include <malloc.h> |
Simon Glass | 2dd337a | 2015-09-02 17:24:58 -0600 | [diff] [blame] | 15 | #include <memalign.h> |
Rene Griessl | 979beee | 2014-11-07 16:53:48 +0100 | [diff] [blame] | 16 | #include <errno.h> |
| 17 | |
| 18 | /* ASIX AX88179 based USB 3.0 Ethernet Devices */ |
| 19 | #define AX88179_PHY_ID 0x03 |
| 20 | #define AX_EEPROM_LEN 0x100 |
| 21 | #define AX88179_EEPROM_MAGIC 0x17900b95 |
| 22 | #define AX_MCAST_FLTSIZE 8 |
| 23 | #define AX_MAX_MCAST 64 |
| 24 | #define AX_INT_PPLS_LINK (1 << 16) |
| 25 | #define AX_RXHDR_L4_TYPE_MASK 0x1c |
| 26 | #define AX_RXHDR_L4_TYPE_UDP 4 |
| 27 | #define AX_RXHDR_L4_TYPE_TCP 16 |
| 28 | #define AX_RXHDR_L3CSUM_ERR 2 |
| 29 | #define AX_RXHDR_L4CSUM_ERR 1 |
| 30 | #define AX_RXHDR_CRC_ERR (1 << 29) |
| 31 | #define AX_RXHDR_DROP_ERR (1 << 31) |
| 32 | #define AX_ENDPOINT_INT 0x01 |
| 33 | #define AX_ENDPOINT_IN 0x02 |
| 34 | #define AX_ENDPOINT_OUT 0x03 |
| 35 | #define AX_ACCESS_MAC 0x01 |
| 36 | #define AX_ACCESS_PHY 0x02 |
| 37 | #define AX_ACCESS_EEPROM 0x04 |
| 38 | #define AX_ACCESS_EFUS 0x05 |
| 39 | #define AX_PAUSE_WATERLVL_HIGH 0x54 |
| 40 | #define AX_PAUSE_WATERLVL_LOW 0x55 |
| 41 | |
| 42 | #define PHYSICAL_LINK_STATUS 0x02 |
| 43 | #define AX_USB_SS (1 << 2) |
| 44 | #define AX_USB_HS (1 << 1) |
| 45 | |
| 46 | #define GENERAL_STATUS 0x03 |
| 47 | #define AX_SECLD (1 << 2) |
| 48 | |
| 49 | #define AX_SROM_ADDR 0x07 |
| 50 | #define AX_SROM_CMD 0x0a |
| 51 | #define EEP_RD (1 << 2) |
| 52 | #define EEP_BUSY (1 << 4) |
| 53 | |
| 54 | #define AX_SROM_DATA_LOW 0x08 |
| 55 | #define AX_SROM_DATA_HIGH 0x09 |
| 56 | |
| 57 | #define AX_RX_CTL 0x0b |
| 58 | #define AX_RX_CTL_DROPCRCERR (1 << 8) |
| 59 | #define AX_RX_CTL_IPE (1 << 9) |
| 60 | #define AX_RX_CTL_START (1 << 7) |
| 61 | #define AX_RX_CTL_AP (1 << 5) |
| 62 | #define AX_RX_CTL_AM (1 << 4) |
| 63 | #define AX_RX_CTL_AB (1 << 3) |
| 64 | #define AX_RX_CTL_AMALL (1 << 1) |
| 65 | #define AX_RX_CTL_PRO (1 << 0) |
| 66 | #define AX_RX_CTL_STOP 0 |
| 67 | |
| 68 | #define AX_NODE_ID 0x10 |
| 69 | #define AX_MULFLTARY 0x16 |
| 70 | |
| 71 | #define AX_MEDIUM_STATUS_MODE 0x22 |
| 72 | #define AX_MEDIUM_GIGAMODE (1 << 0) |
| 73 | #define AX_MEDIUM_FULL_DUPLEX (1 << 1) |
| 74 | #define AX_MEDIUM_EN_125MHZ (1 << 3) |
| 75 | #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4) |
| 76 | #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5) |
| 77 | #define AX_MEDIUM_RECEIVE_EN (1 << 8) |
| 78 | #define AX_MEDIUM_PS (1 << 9) |
| 79 | #define AX_MEDIUM_JUMBO_EN 0x8040 |
| 80 | |
| 81 | #define AX_MONITOR_MOD 0x24 |
| 82 | #define AX_MONITOR_MODE_RWLC (1 << 1) |
| 83 | #define AX_MONITOR_MODE_RWMP (1 << 2) |
| 84 | #define AX_MONITOR_MODE_PMEPOL (1 << 5) |
| 85 | #define AX_MONITOR_MODE_PMETYPE (1 << 6) |
| 86 | |
| 87 | #define AX_GPIO_CTRL 0x25 |
| 88 | #define AX_GPIO_CTRL_GPIO3EN (1 << 7) |
| 89 | #define AX_GPIO_CTRL_GPIO2EN (1 << 6) |
| 90 | #define AX_GPIO_CTRL_GPIO1EN (1 << 5) |
| 91 | |
| 92 | #define AX_PHYPWR_RSTCTL 0x26 |
| 93 | #define AX_PHYPWR_RSTCTL_BZ (1 << 4) |
| 94 | #define AX_PHYPWR_RSTCTL_IPRL (1 << 5) |
| 95 | #define AX_PHYPWR_RSTCTL_AT (1 << 12) |
| 96 | |
| 97 | #define AX_RX_BULKIN_QCTRL 0x2e |
| 98 | #define AX_CLK_SELECT 0x33 |
| 99 | #define AX_CLK_SELECT_BCS (1 << 0) |
| 100 | #define AX_CLK_SELECT_ACS (1 << 1) |
| 101 | #define AX_CLK_SELECT_ULR (1 << 3) |
| 102 | |
| 103 | #define AX_RXCOE_CTL 0x34 |
| 104 | #define AX_RXCOE_IP (1 << 0) |
| 105 | #define AX_RXCOE_TCP (1 << 1) |
| 106 | #define AX_RXCOE_UDP (1 << 2) |
| 107 | #define AX_RXCOE_TCPV6 (1 << 5) |
| 108 | #define AX_RXCOE_UDPV6 (1 << 6) |
| 109 | |
| 110 | #define AX_TXCOE_CTL 0x35 |
| 111 | #define AX_TXCOE_IP (1 << 0) |
| 112 | #define AX_TXCOE_TCP (1 << 1) |
| 113 | #define AX_TXCOE_UDP (1 << 2) |
| 114 | #define AX_TXCOE_TCPV6 (1 << 5) |
| 115 | #define AX_TXCOE_UDPV6 (1 << 6) |
| 116 | |
| 117 | #define AX_LEDCTRL 0x73 |
| 118 | |
| 119 | #define GMII_PHY_PHYSR 0x11 |
| 120 | #define GMII_PHY_PHYSR_SMASK 0xc000 |
| 121 | #define GMII_PHY_PHYSR_GIGA (1 << 15) |
| 122 | #define GMII_PHY_PHYSR_100 (1 << 14) |
| 123 | #define GMII_PHY_PHYSR_FULL (1 << 13) |
| 124 | #define GMII_PHY_PHYSR_LINK (1 << 10) |
| 125 | |
| 126 | #define GMII_LED_ACT 0x1a |
| 127 | #define GMII_LED_ACTIVE_MASK 0xff8f |
| 128 | #define GMII_LED0_ACTIVE (1 << 4) |
| 129 | #define GMII_LED1_ACTIVE (1 << 5) |
| 130 | #define GMII_LED2_ACTIVE (1 << 6) |
| 131 | |
| 132 | #define GMII_LED_LINK 0x1c |
| 133 | #define GMII_LED_LINK_MASK 0xf888 |
| 134 | #define GMII_LED0_LINK_10 (1 << 0) |
| 135 | #define GMII_LED0_LINK_100 (1 << 1) |
| 136 | #define GMII_LED0_LINK_1000 (1 << 2) |
| 137 | #define GMII_LED1_LINK_10 (1 << 4) |
| 138 | #define GMII_LED1_LINK_100 (1 << 5) |
| 139 | #define GMII_LED1_LINK_1000 (1 << 6) |
| 140 | #define GMII_LED2_LINK_10 (1 << 8) |
| 141 | #define GMII_LED2_LINK_100 (1 << 9) |
| 142 | #define GMII_LED2_LINK_1000 (1 << 10) |
| 143 | #define LED0_ACTIVE (1 << 0) |
| 144 | #define LED0_LINK_10 (1 << 1) |
| 145 | #define LED0_LINK_100 (1 << 2) |
| 146 | #define LED0_LINK_1000 (1 << 3) |
| 147 | #define LED0_FD (1 << 4) |
| 148 | #define LED0_USB3_MASK 0x001f |
| 149 | #define LED1_ACTIVE (1 << 5) |
| 150 | #define LED1_LINK_10 (1 << 6) |
| 151 | #define LED1_LINK_100 (1 << 7) |
| 152 | #define LED1_LINK_1000 (1 << 8) |
| 153 | #define LED1_FD (1 << 9) |
| 154 | #define LED1_USB3_MASK 0x03e0 |
| 155 | #define LED2_ACTIVE (1 << 10) |
| 156 | #define LED2_LINK_1000 (1 << 13) |
| 157 | #define LED2_LINK_100 (1 << 12) |
| 158 | #define LED2_LINK_10 (1 << 11) |
| 159 | #define LED2_FD (1 << 14) |
| 160 | #define LED_VALID (1 << 15) |
| 161 | #define LED2_USB3_MASK 0x7c00 |
| 162 | |
| 163 | #define GMII_PHYPAGE 0x1e |
| 164 | #define GMII_PHY_PAGE_SELECT 0x1f |
| 165 | #define GMII_PHY_PGSEL_EXT 0x0007 |
| 166 | #define GMII_PHY_PGSEL_PAGE0 0x0000 |
| 167 | |
| 168 | /* local defines */ |
| 169 | #define ASIX_BASE_NAME "axg" |
| 170 | #define USB_CTRL_SET_TIMEOUT 5000 |
| 171 | #define USB_CTRL_GET_TIMEOUT 5000 |
| 172 | #define USB_BULK_SEND_TIMEOUT 5000 |
| 173 | #define USB_BULK_RECV_TIMEOUT 5000 |
| 174 | |
| 175 | #define AX_RX_URB_SIZE 1024 * 0x12 |
| 176 | #define BLK_FRAME_SIZE 0x200 |
| 177 | #define PHY_CONNECT_TIMEOUT 5000 |
| 178 | |
| 179 | #define TIMEOUT_RESOLUTION 50 /* ms */ |
| 180 | |
| 181 | #define FLAG_NONE 0 |
| 182 | #define FLAG_TYPE_AX88179 (1U << 0) |
| 183 | #define FLAG_TYPE_AX88178a (1U << 1) |
| 184 | #define FLAG_TYPE_DLINK_DUB1312 (1U << 2) |
| 185 | #define FLAG_TYPE_SITECOM (1U << 3) |
| 186 | #define FLAG_TYPE_SAMSUNG (1U << 4) |
| 187 | #define FLAG_TYPE_LENOVO (1U << 5) |
| 188 | |
| 189 | /* local vars */ |
| 190 | static const struct { |
| 191 | unsigned char ctrl, timer_l, timer_h, size, ifg; |
| 192 | } AX88179_BULKIN_SIZE[] = { |
| 193 | {7, 0x4f, 0, 0x02, 0xff}, |
| 194 | {7, 0x20, 3, 0x03, 0xff}, |
| 195 | {7, 0xae, 7, 0x04, 0xff}, |
| 196 | {7, 0xcc, 0x4c, 0x04, 8}, |
| 197 | }; |
| 198 | |
| 199 | static int curr_eth_dev; /* index for name of next device detected */ |
| 200 | |
| 201 | /* driver private */ |
| 202 | struct asix_private { |
| 203 | int flags; |
| 204 | int rx_urb_size; |
| 205 | int maxpacketsize; |
| 206 | }; |
| 207 | |
| 208 | /* |
| 209 | * Asix infrastructure commands |
| 210 | */ |
| 211 | static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, |
| 212 | u16 size, void *data) |
| 213 | { |
| 214 | int len; |
| 215 | ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); |
| 216 | |
| 217 | debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", |
| 218 | cmd, value, index, size); |
| 219 | |
| 220 | memcpy(buf, data, size); |
| 221 | |
| 222 | len = usb_control_msg( |
| 223 | dev->pusb_dev, |
| 224 | usb_sndctrlpipe(dev->pusb_dev, 0), |
| 225 | cmd, |
| 226 | USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, |
| 227 | value, |
| 228 | index, |
| 229 | buf, |
| 230 | size, |
| 231 | USB_CTRL_SET_TIMEOUT); |
| 232 | |
| 233 | return len == size ? 0 : ECOMM; |
| 234 | } |
| 235 | |
| 236 | static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, |
| 237 | u16 size, void *data) |
| 238 | { |
| 239 | int len; |
| 240 | ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); |
| 241 | |
| 242 | debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", |
| 243 | cmd, value, index, size); |
| 244 | |
| 245 | len = usb_control_msg( |
| 246 | dev->pusb_dev, |
| 247 | usb_rcvctrlpipe(dev->pusb_dev, 0), |
| 248 | cmd, |
| 249 | USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, |
| 250 | value, |
| 251 | index, |
| 252 | buf, |
| 253 | size, |
| 254 | USB_CTRL_GET_TIMEOUT); |
| 255 | |
| 256 | memcpy(data, buf, size); |
| 257 | |
| 258 | return len == size ? 0 : ECOMM; |
| 259 | } |
| 260 | |
| 261 | static int asix_read_mac(struct eth_device *eth) |
| 262 | { |
| 263 | struct ueth_data *dev = (struct ueth_data *)eth->priv; |
| 264 | u8 buf[ETH_ALEN]; |
| 265 | |
| 266 | asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, buf); |
| 267 | debug("asix_read_mac() returning %02x:%02x:%02x:%02x:%02x:%02x\n", |
| 268 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); |
| 269 | |
| 270 | memcpy(eth->enetaddr, buf, ETH_ALEN); |
| 271 | |
| 272 | return 0; |
| 273 | } |
| 274 | |
Rene Griessl | eecc3ce | 2015-01-12 17:51:16 +0100 | [diff] [blame] | 275 | static int asix_write_mac(struct eth_device *eth) |
| 276 | { |
| 277 | struct ueth_data *dev = (struct ueth_data *)eth->priv; |
| 278 | int ret; |
| 279 | |
| 280 | ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, |
| 281 | ETH_ALEN, eth->enetaddr); |
| 282 | if (ret < 0) |
| 283 | debug("Failed to set MAC address: %02x\n", ret); |
| 284 | |
| 285 | return ret; |
| 286 | } |
| 287 | |
Rene Griessl | 979beee | 2014-11-07 16:53:48 +0100 | [diff] [blame] | 288 | static int asix_basic_reset(struct ueth_data *dev) |
| 289 | { |
| 290 | struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; |
| 291 | u8 buf[5]; |
| 292 | u16 *tmp16; |
| 293 | u8 *tmp; |
| 294 | |
| 295 | tmp16 = (u16 *)buf; |
| 296 | tmp = (u8 *)buf; |
| 297 | |
| 298 | /* Power up ethernet PHY */ |
| 299 | *tmp16 = 0; |
| 300 | asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); |
| 301 | |
| 302 | *tmp16 = AX_PHYPWR_RSTCTL_IPRL; |
| 303 | asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); |
| 304 | mdelay(200); |
| 305 | |
| 306 | *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; |
| 307 | asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); |
| 308 | mdelay(200); |
| 309 | |
| 310 | /* RX bulk configuration */ |
| 311 | memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); |
| 312 | asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); |
| 313 | |
| 314 | dev_priv->rx_urb_size = 128 * 20; |
| 315 | |
| 316 | /* Water Level configuration */ |
| 317 | *tmp = 0x34; |
| 318 | asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); |
| 319 | |
| 320 | *tmp = 0x52; |
| 321 | asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp); |
| 322 | |
| 323 | /* Enable checksum offload */ |
| 324 | *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | |
| 325 | AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; |
| 326 | asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); |
| 327 | |
| 328 | *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | |
| 329 | AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; |
| 330 | asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); |
| 331 | |
| 332 | /* Configure RX control register => start operation */ |
| 333 | *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | |
| 334 | AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; |
| 335 | asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); |
| 336 | |
| 337 | *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | |
| 338 | AX_MONITOR_MODE_RWMP; |
| 339 | asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); |
| 340 | |
| 341 | /* Configure default medium type => giga */ |
| 342 | *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | |
| 343 | AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | |
| 344 | AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN; |
| 345 | asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16); |
| 346 | |
| 347 | u16 adv = 0; |
| 348 | adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK | |
| 349 | ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP; |
| 350 | asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv); |
| 351 | |
| 352 | adv = ADVERTISE_1000FULL; |
| 353 | asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv); |
| 354 | |
| 355 | return 0; |
| 356 | } |
| 357 | |
| 358 | static int asix_wait_link(struct ueth_data *dev) |
| 359 | { |
| 360 | int timeout = 0; |
| 361 | int link_detected; |
| 362 | u8 buf[2]; |
| 363 | u16 *tmp16; |
| 364 | |
| 365 | tmp16 = (u16 *)buf; |
| 366 | |
| 367 | do { |
| 368 | asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, |
| 369 | MII_BMSR, 2, buf); |
| 370 | link_detected = *tmp16 & BMSR_LSTATUS; |
| 371 | if (!link_detected) { |
| 372 | if (timeout == 0) |
| 373 | printf("Waiting for Ethernet connection... "); |
| 374 | mdelay(TIMEOUT_RESOLUTION); |
| 375 | timeout += TIMEOUT_RESOLUTION; |
| 376 | } |
| 377 | } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); |
| 378 | |
| 379 | if (link_detected) { |
| 380 | if (timeout > 0) |
| 381 | printf("done.\n"); |
| 382 | return 0; |
| 383 | } else { |
| 384 | printf("unable to connect.\n"); |
| 385 | return -ENETUNREACH; |
| 386 | } |
| 387 | } |
| 388 | |
| 389 | /* |
| 390 | * Asix callbacks |
| 391 | */ |
| 392 | static int asix_init(struct eth_device *eth, bd_t *bd) |
| 393 | { |
| 394 | struct ueth_data *dev = (struct ueth_data *)eth->priv; |
| 395 | struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; |
| 396 | u8 buf[2], tmp[5], link_sts; |
| 397 | u16 *tmp16, mode; |
| 398 | |
| 399 | |
| 400 | tmp16 = (u16 *)buf; |
| 401 | |
| 402 | debug("** %s()\n", __func__); |
| 403 | |
| 404 | /* Configure RX control register => start operation */ |
| 405 | *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | |
| 406 | AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; |
| 407 | if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0) |
| 408 | goto out_err; |
| 409 | |
| 410 | if (asix_wait_link(dev) != 0) { |
| 411 | /*reset device and try again*/ |
| 412 | printf("Reset Ethernet Device\n"); |
| 413 | asix_basic_reset(dev); |
| 414 | if (asix_wait_link(dev) != 0) |
| 415 | goto out_err; |
| 416 | } |
| 417 | |
| 418 | /* Configure link */ |
| 419 | mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | |
| 420 | AX_MEDIUM_RXFLOW_CTRLEN; |
| 421 | |
| 422 | asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS, |
| 423 | 1, 1, &link_sts); |
| 424 | |
| 425 | asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, |
| 426 | GMII_PHY_PHYSR, 2, tmp16); |
| 427 | |
| 428 | if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) { |
| 429 | return 0; |
| 430 | } else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { |
| 431 | mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ | |
| 432 | AX_MEDIUM_JUMBO_EN; |
| 433 | |
| 434 | if (link_sts & AX_USB_SS) |
| 435 | memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); |
| 436 | else if (link_sts & AX_USB_HS) |
| 437 | memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5); |
| 438 | else |
| 439 | memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); |
| 440 | } else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { |
| 441 | mode |= AX_MEDIUM_PS; |
| 442 | |
| 443 | if (link_sts & (AX_USB_SS | AX_USB_HS)) |
| 444 | memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5); |
| 445 | else |
| 446 | memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); |
| 447 | } else { |
| 448 | memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); |
| 449 | } |
| 450 | |
| 451 | /* RX bulk configuration */ |
| 452 | asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); |
| 453 | |
| 454 | dev_priv->rx_urb_size = (1024 * (tmp[3] + 2)); |
| 455 | if (*tmp16 & GMII_PHY_PHYSR_FULL) |
| 456 | mode |= AX_MEDIUM_FULL_DUPLEX; |
| 457 | asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, |
| 458 | 2, 2, &mode); |
| 459 | |
| 460 | return 0; |
| 461 | out_err: |
| 462 | return -1; |
| 463 | } |
| 464 | |
| 465 | static int asix_send(struct eth_device *eth, void *packet, int length) |
| 466 | { |
| 467 | struct ueth_data *dev = (struct ueth_data *)eth->priv; |
| 468 | struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; |
| 469 | |
| 470 | int err; |
| 471 | u32 packet_len, tx_hdr2; |
| 472 | int actual_len, framesize; |
| 473 | ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, |
| 474 | PKTSIZE + (2 * sizeof(packet_len))); |
| 475 | |
| 476 | debug("** %s(), len %d\n", __func__, length); |
| 477 | |
| 478 | packet_len = length; |
| 479 | cpu_to_le32s(&packet_len); |
| 480 | |
| 481 | memcpy(msg, &packet_len, sizeof(packet_len)); |
| 482 | framesize = dev_priv->maxpacketsize; |
| 483 | tx_hdr2 = 0; |
| 484 | if (((length + 8) % framesize) == 0) |
| 485 | tx_hdr2 |= 0x80008000; /* Enable padding */ |
| 486 | |
| 487 | cpu_to_le32s(&tx_hdr2); |
| 488 | |
| 489 | memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2)); |
| 490 | |
| 491 | memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2), |
| 492 | (void *)packet, length); |
| 493 | |
| 494 | err = usb_bulk_msg(dev->pusb_dev, |
| 495 | usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), |
| 496 | (void *)msg, |
| 497 | length + sizeof(packet_len) + sizeof(tx_hdr2), |
| 498 | &actual_len, |
| 499 | USB_BULK_SEND_TIMEOUT); |
Mateusz Kulikowski | d3b2359 | 2016-03-31 23:12:22 +0200 | [diff] [blame] | 500 | debug("Tx: len = %zu, actual = %u, err = %d\n", |
Rene Griessl | 979beee | 2014-11-07 16:53:48 +0100 | [diff] [blame] | 501 | length + sizeof(packet_len), actual_len, err); |
| 502 | |
| 503 | return err; |
| 504 | } |
| 505 | |
| 506 | static int asix_recv(struct eth_device *eth) |
| 507 | { |
| 508 | struct ueth_data *dev = (struct ueth_data *)eth->priv; |
| 509 | struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; |
| 510 | |
| 511 | u16 frame_pos; |
| 512 | int err; |
| 513 | int actual_len; |
| 514 | |
| 515 | int pkt_cnt; |
| 516 | u32 rx_hdr; |
| 517 | u16 hdr_off; |
| 518 | u32 *pkt_hdr; |
| 519 | ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size); |
| 520 | |
| 521 | actual_len = -1; |
| 522 | |
| 523 | debug("** %s()\n", __func__); |
| 524 | |
| 525 | err = usb_bulk_msg(dev->pusb_dev, |
| 526 | usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), |
| 527 | (void *)recv_buf, |
| 528 | dev_priv->rx_urb_size, |
| 529 | &actual_len, |
| 530 | USB_BULK_RECV_TIMEOUT); |
| 531 | debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size, |
| 532 | actual_len, err); |
| 533 | |
| 534 | if (err != 0) { |
| 535 | debug("Rx: failed to receive\n"); |
| 536 | return -ECOMM; |
| 537 | } |
| 538 | if (actual_len > dev_priv->rx_urb_size) { |
| 539 | debug("Rx: received too many bytes %d\n", actual_len); |
| 540 | return -EMSGSIZE; |
| 541 | } |
| 542 | |
| 543 | |
| 544 | rx_hdr = *(u32 *)(recv_buf + actual_len - 4); |
| 545 | le32_to_cpus(&pkt_hdr); |
| 546 | |
| 547 | pkt_cnt = (u16)rx_hdr; |
| 548 | hdr_off = (u16)(rx_hdr >> 16); |
| 549 | pkt_hdr = (u32 *)(recv_buf + hdr_off); |
| 550 | |
| 551 | |
| 552 | frame_pos = 0; |
| 553 | |
| 554 | while (pkt_cnt--) { |
| 555 | u16 pkt_len; |
| 556 | |
| 557 | le32_to_cpus(pkt_hdr); |
| 558 | pkt_len = (*pkt_hdr >> 16) & 0x1fff; |
| 559 | |
| 560 | frame_pos += 2; |
| 561 | |
Joe Hershberger | 9f09a36 | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 562 | net_process_received_packet(recv_buf + frame_pos, pkt_len); |
Rene Griessl | 979beee | 2014-11-07 16:53:48 +0100 | [diff] [blame] | 563 | |
| 564 | pkt_hdr++; |
| 565 | frame_pos += ((pkt_len + 7) & 0xFFF8)-2; |
| 566 | |
| 567 | if (pkt_cnt == 0) |
| 568 | return 0; |
| 569 | } |
| 570 | return err; |
| 571 | } |
| 572 | |
| 573 | static void asix_halt(struct eth_device *eth) |
| 574 | { |
| 575 | debug("** %s()\n", __func__); |
| 576 | } |
| 577 | |
| 578 | /* |
| 579 | * Asix probing functions |
| 580 | */ |
| 581 | void ax88179_eth_before_probe(void) |
| 582 | { |
| 583 | curr_eth_dev = 0; |
| 584 | } |
| 585 | |
| 586 | struct asix_dongle { |
| 587 | unsigned short vendor; |
| 588 | unsigned short product; |
| 589 | int flags; |
| 590 | }; |
| 591 | |
| 592 | static const struct asix_dongle asix_dongles[] = { |
| 593 | { 0x0b95, 0x1790, FLAG_TYPE_AX88179 }, |
| 594 | { 0x0b95, 0x178a, FLAG_TYPE_AX88178a }, |
| 595 | { 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 }, |
| 596 | { 0x0df6, 0x0072, FLAG_TYPE_SITECOM }, |
| 597 | { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG }, |
| 598 | { 0x17ef, 0x304b, FLAG_TYPE_LENOVO }, |
| 599 | { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */ |
| 600 | }; |
| 601 | |
| 602 | /* Probe to see if a new device is actually an asix device */ |
| 603 | int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum, |
| 604 | struct ueth_data *ss) |
| 605 | { |
| 606 | struct usb_interface *iface; |
| 607 | struct usb_interface_descriptor *iface_desc; |
| 608 | struct asix_private *dev_priv; |
| 609 | int ep_in_found = 0, ep_out_found = 0; |
| 610 | int i; |
| 611 | |
| 612 | /* let's examine the device now */ |
| 613 | iface = &dev->config.if_desc[ifnum]; |
| 614 | iface_desc = &dev->config.if_desc[ifnum].desc; |
| 615 | |
| 616 | for (i = 0; asix_dongles[i].vendor != 0; i++) { |
| 617 | if (dev->descriptor.idVendor == asix_dongles[i].vendor && |
| 618 | dev->descriptor.idProduct == asix_dongles[i].product) |
| 619 | /* Found a supported dongle */ |
| 620 | break; |
| 621 | } |
| 622 | |
| 623 | if (asix_dongles[i].vendor == 0) |
| 624 | return 0; |
| 625 | |
| 626 | memset(ss, 0, sizeof(struct ueth_data)); |
| 627 | |
| 628 | /* At this point, we know we've got a live one */ |
| 629 | debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", |
| 630 | dev->descriptor.idVendor, dev->descriptor.idProduct); |
| 631 | |
| 632 | /* Initialize the ueth_data structure with some useful info */ |
| 633 | ss->ifnum = ifnum; |
| 634 | ss->pusb_dev = dev; |
| 635 | ss->subclass = iface_desc->bInterfaceSubClass; |
| 636 | ss->protocol = iface_desc->bInterfaceProtocol; |
| 637 | |
| 638 | /* alloc driver private */ |
| 639 | ss->dev_priv = calloc(1, sizeof(struct asix_private)); |
| 640 | if (!ss->dev_priv) |
| 641 | return 0; |
| 642 | dev_priv = ss->dev_priv; |
| 643 | dev_priv->flags = asix_dongles[i].flags; |
| 644 | |
| 645 | /* |
| 646 | * We are expecting a minimum of 3 endpoints - in, out (bulk), and |
| 647 | * int. We will ignore any others. |
| 648 | */ |
| 649 | for (i = 0; i < iface_desc->bNumEndpoints; i++) { |
| 650 | /* is it an interrupt endpoint? */ |
| 651 | if ((iface->ep_desc[i].bmAttributes & |
| 652 | USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { |
| 653 | ss->ep_int = iface->ep_desc[i].bEndpointAddress & |
| 654 | USB_ENDPOINT_NUMBER_MASK; |
| 655 | ss->irqinterval = iface->ep_desc[i].bInterval; |
| 656 | continue; |
| 657 | } |
| 658 | |
| 659 | /* is it an BULK endpoint? */ |
| 660 | if (!((iface->ep_desc[i].bmAttributes & |
| 661 | USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK)) |
| 662 | continue; |
| 663 | |
| 664 | u8 ep_addr = iface->ep_desc[i].bEndpointAddress; |
| 665 | if ((ep_addr & USB_DIR_IN) && !ep_in_found) { |
| 666 | ss->ep_in = ep_addr & |
| 667 | USB_ENDPOINT_NUMBER_MASK; |
| 668 | ep_in_found = 1; |
| 669 | } |
| 670 | if (!(ep_addr & USB_DIR_IN) && !ep_out_found) { |
| 671 | ss->ep_out = ep_addr & |
| 672 | USB_ENDPOINT_NUMBER_MASK; |
| 673 | dev_priv->maxpacketsize = |
| 674 | dev->epmaxpacketout[AX_ENDPOINT_OUT]; |
| 675 | ep_out_found = 1; |
| 676 | } |
| 677 | } |
| 678 | debug("Endpoints In %d Out %d Int %d\n", |
| 679 | ss->ep_in, ss->ep_out, ss->ep_int); |
| 680 | |
| 681 | /* Do some basic sanity checks, and bail if we find a problem */ |
| 682 | if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || |
| 683 | !ss->ep_in || !ss->ep_out || !ss->ep_int) { |
| 684 | debug("Problems with device\n"); |
| 685 | return 0; |
| 686 | } |
| 687 | dev->privptr = (void *)ss; |
| 688 | return 1; |
| 689 | } |
| 690 | |
| 691 | int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, |
| 692 | struct eth_device *eth) |
| 693 | { |
| 694 | if (!eth) { |
| 695 | debug("%s: missing parameter.\n", __func__); |
| 696 | return 0; |
| 697 | } |
| 698 | sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++); |
| 699 | eth->init = asix_init; |
| 700 | eth->send = asix_send; |
| 701 | eth->recv = asix_recv; |
| 702 | eth->halt = asix_halt; |
Rene Griessl | eecc3ce | 2015-01-12 17:51:16 +0100 | [diff] [blame] | 703 | eth->write_hwaddr = asix_write_mac; |
Rene Griessl | 979beee | 2014-11-07 16:53:48 +0100 | [diff] [blame] | 704 | eth->priv = ss; |
| 705 | |
| 706 | if (asix_basic_reset(ss)) |
| 707 | return 0; |
| 708 | |
| 709 | /* Get the MAC address */ |
| 710 | if (asix_read_mac(eth)) |
| 711 | return 0; |
| 712 | debug("MAC %pM\n", eth->enetaddr); |
| 713 | |
| 714 | return 1; |
| 715 | } |