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git01.mediatek.com / filogic / uboot / 66ca25cf507b4532f3f2b6c4b0aad337028921bb / . / drivers / clk / mediatek / clk-mt7981.c
blob: 7fcb81419cdee889d4e31ae4541975177edcc8e9 [file] [log] [blame]
developer79128da2022-09-09 20:00:12 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek clock driver for MT7981 SoC
4 *
5 * Copyright (C) 2022 MediaTek Inc.
6 * Author: Sam Shih <sam.shih@mediatek.com>
7 */
8
9#include <dm.h>
10#include <log.h>
11#include <asm/arch-mediatek/reset.h>
12#include <asm/io.h>
13#include <dt-bindings/clock/mt7981-clk.h>
14#include <linux/bitops.h>
15
16#include "clk-mtk.h"
17
18#define MT7981_CLK_PDN 0x250
19#define MT7981_CLK_PDN_EN_WRITE BIT(31)
20
21#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \
22 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
23
24#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \
25 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
26
27#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \
28 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
29
30/* FIXED PLLS */
31static const struct mtk_fixed_clk fixed_pll_clks[] = {
32 FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 1300000000),
33 FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
34 FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
35 FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
36 FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
37 FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
38 FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
39 FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
40};
41
42/* TOPCKGEN FIXED CLK */
43static const struct mtk_fixed_clk top_fixed_clks[] = {
44 FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
45};
46
47/* TOPCKGEN FIXED DIV */
48static const struct mtk_fixed_factor top_fixed_divs[] = {
49 PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
50 PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
51 PLL_FACTOR(CK_TOP_CB_M_D3, "cb_m_d3", CK_APMIXED_MPLL, 1, 3),
52 PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
53 PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
54 PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
55 PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
56 PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
57 PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
58 PLL_FACTOR(CK_TOP_CB_MM_D3, "cb_mm_d3", CK_APMIXED_MMPLL, 1, 3),
59 PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
60 PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
61 PLL_FACTOR(CK_TOP_CB_MM_D6, "cb_mm_d6", CK_APMIXED_MMPLL, 1, 6),
62 PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
63 PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
64 PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
65 1),
66 PLL_FACTOR(CK_TOP_APLL2_D2, "apll2_d2", CK_APMIXED_APLL2, 1, 2),
67 PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
68 PLL_FACTOR(CK_TOP_NET1_2500M, "net1_2500m", CK_APMIXED_NET1PLL, 1, 1),
69 PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
70 PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
71 PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
72 PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
73 PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
74 PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
75 PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
76 PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
77 1),
78 PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
79 PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
80 PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
81 PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
82 PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
83 PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
84 CK_APMIXED_WEDMCUPLL, 1, 1),
85 PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
86 TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
87 TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
88 1250),
89 TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
90 1220),
91 TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1),
92 TOP_FACTOR(CK_TOP_FAUD, "faud", CK_TOP_CB_CKSQ_40M, 1, 1),
93 TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
94 TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1,
95 1),
96 TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1),
97 TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1),
98 TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
99 TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
100 TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
101 TOP_FACTOR(CK_TOP_UART_BCK, "uart_bck", CK_TOP_UART_SEL, 1, 1),
102 TOP_FACTOR(CK_TOP_PWM_BCK, "pwm_bck", CK_TOP_PWM_SEL, 1, 1),
103 TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
104 TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
105 TOP_FACTOR(CK_TOP_EMMC_208M, "emmc_208m", CK_TOP_EMMC_208M_SEL, 1, 1),
106 TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
107 TOP_FACTOR(CK_TOP_DRAMC_REF, "dramc_ref", CK_TOP_DRAMC_SEL, 1, 1),
108 TOP_FACTOR(CK_TOP_DRAMC_MD32, "dramc_md32", CK_TOP_DRAMC_MD32_SEL, 1,
109 1),
110 TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
111 TOP_FACTOR(CK_TOP_SYSAPB, "sysapb", CK_TOP_SYSAPB_SEL, 1, 1),
112 TOP_FACTOR(CK_TOP_ARM_DB_MAIN, "arm_db_main", CK_TOP_ARM_DB_MAIN_SEL, 1,
113 1),
114 TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
115 1),
116 TOP_FACTOR(CK_TOP_NETSYS, "netsys", CK_TOP_NETSYS_SEL, 1, 1),
117 TOP_FACTOR(CK_TOP_NETSYS_500M, "netsys_500m", CK_TOP_NETSYS_500M_SEL, 1,
118 1),
119 TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
120 CK_TOP_NETSYS_MCU_SEL, 1, 1),
121 TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
122 TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
123 TOP_FACTOR(CK_TOP_SGM_REG, "sgm_reg", CK_TOP_SGM_REG_SEL, 1, 1),
124 TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
125 TOP_FACTOR(CK_TOP_EIP97B, "eip97b", CK_TOP_EIP97B_SEL, 1, 1),
126 TOP_FACTOR(CK_TOP_USB3_PHY, "usb3_phy", CK_TOP_USB3_PHY_SEL, 1, 1),
127 TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_FAUD, 1, 1),
128 TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
129 TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
130 TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
131 TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
132 TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
133 TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
134 TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
135 1),
136};
137
138/* TOPCKGEN MUX PARENTS */
139static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
140 CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6,
141 CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8,
142 CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
143
144static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
145 CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
146 CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
147 CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 };
148
149static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
150 CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
151 CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4,
152 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
153
154static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
155 CK_TOP_M_D8_D2 };
156
157static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
158 CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
159 CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
160
161static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
162 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
163
164static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
165 CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
166 CK_TOP_CB_RTC_32K };
167
168static const int emmc_208m_parents[] = {
169 CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, CK_TOP_CB_NET2_D4,
170 CK_TOP_CB_APLL2_196M, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
171 CK_TOP_CB_MM_D6
172};
173
174static const int emmc_400m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
175 CK_TOP_CB_MM_D2, CK_TOP_CB_NET2_D2 };
176
177static const int csw_f26m_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
178
179static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
180 CK_TOP_CB_WEDMCU_208M };
181
182static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2 };
183
184static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
185
186static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M,
187 CK_TOP_CB_NET2_D6 };
188
189static const int ap2cnn_host_parents[] = { CK_TOP_CB_CKSQ_40M,
190 CK_TOP_NET1_D8_D4 };
191
192static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D2 };
193
194static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
195 CK_TOP_CB_NET1_D5 };
196
197static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_720M,
198 CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5,
199 CK_TOP_CB_M_416M };
200
201static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
202 CK_TOP_CB_NET2_800M,
203 CK_TOP_CB_MM_720M };
204
205static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M,
206 CK_TOP_CB_SGM_325M };
207
208static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D4 };
209
210static const int eip97b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
211 CK_TOP_CB_M_416M, CK_TOP_CB_MM_D2,
212 CK_TOP_NET1_D5_D2 };
213
214static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
215
216static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
217
218static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
219 CK_TOP_M_D8_D2 };
220
221static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
222 CK_TOP_M_D8_D2 };
223
224static const int u2u3_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
225
226static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
227
228static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
229 CK_TOP_CB_MM_D3_D5 };
230
231#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
232 _shift, _width, _gate, _upd_ofs, _upd) \
233 { \
234 .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \
235 .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \
236 .upd_shift = _upd, .mux_shift = _shift, \
237 .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
238 .gate_shift = _gate, .parent = _parents, \
239 .num_parents = ARRAY_SIZE(_parents), \
240 .flags = CLK_MUX_SETCLR_UPD, \
241 }
242
243/* TOPCKGEN MUX_GATE */
244static const struct mtk_composite top_muxes[] = {
245 TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0,
246 3, 7, 0x1c0, 0),
247 TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8,
248 8, 3, 15, 0x1c0, 1),
249 TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3,
250 23, 0x1c0, 2),
251 TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8,
252 24, 3, 31, 0x1c0, 3),
253 TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0,
254 2, 7, 0x1c0, 4),
255 TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3,
256 15, 0x1c0, 5),
257 TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2,
258 23, 0x1c0, 6),
259 TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
260 0x10, 0x14, 0x18, 24, 2, 31, 0x1c0, 7),
261 TOP_MUX(CK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20,
262 0x24, 0x28, 0, 3, 7, 0x1c0, 8),
263 TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
264 0x24, 0x28, 8, 2, 15, 0x1c0, 9),
265 TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24,
266 0x28, 16, 1, 23, 0x1c0, 10),
267 TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24,
268 0x28, 24, 1, 31, 0x1c0, 11),
269 TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
270 0x30, 0x34, 0x38, 0, 2, 7, 0x1c0, 12),
271 TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34,
272 0x38, 8, 1, 15, 0x1c0, 13),
273 TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34,
274 0x38, 16, 1, 23, 0x1c0, 14),
275 TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
276 0x30, 0x34, 0x38, 24, 1, 31, 0x1c0, 15),
277 TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents,
278 0x40, 0x44, 0x48, 0, 1, 7, 0x1c0, 16),
279 TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44,
280 0x48, 8, 1, 15, 0x1c0, 17),
281 TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
282 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0, 18),
283 TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
284 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
285 TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50,
286 0x54, 0x58, 0, 2, 7, 0x1c0, 20),
287 TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50,
288 0x54, 0x58, 8, 1, 15, 0x1c0, 21),
289 TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54,
290 0x58, 16, 1, 23, 0x1c0, 22),
291 TOP_MUX(CK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54,
292 0x58, 24, 3, 31, 0x1c0, 23),
293 TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60,
294 0x64, 0x68, 0, 1, 7, 0x1c0, 24),
295 TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1,
296 15, 0x1c0, 25),
297 TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68,
298 16, 1, 23, 0x1c0, 26),
299 TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68,
300 24, 2, 31, 0x1c0, 27),
301 TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74,
302 0x78, 0, 2, 7, 0x1c0, 28),
303 TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8,
304 1, 15, 0x1c0, 29),
305 TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70,
306 0x74, 0x78, 16, 1, 23, 0x1c0, 30),
307 TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70,
308 0x74, 0x78, 24, 1, 31, 0x1c4, 0),
309 TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
310 0x80, 0x84, 0x88, 0, 1, 7, 0x1c4, 1),
311};
312
313/* INFRA FIXED DIV */
314static const struct mtk_fixed_factor infra_fixed_divs[] = {
315 TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1),
316 TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1),
317 TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1),
318 TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1),
319 TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPIM_MST_SEL, 1, 1),
320 TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
321 TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2),
322 TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1,
323 1),
324 TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1),
325 INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1,
326 1),
327 INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1,
328 1),
329 INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1,
330 1),
331 TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
332 INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
333 1),
334 TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1),
335 TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1),
336 TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1,
337 1),
338 TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1),
339 INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL,
340 1, 1),
341 INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL,
342 1, 1),
343 INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL,
344 1, 1),
345 TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1),
346 TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1),
347 INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1,
348 1),
349 INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1,
350 1),
351 INFRA_FACTOR(CK_INFRA_MUX_SPI2, "infra_mux_spi2", CK_INFRA_SPI2_SEL, 1,
352 1),
353 TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1),
354 TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_400M, 1, 1),
355 TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_208M,
356 1, 1),
357 TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
358 TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1),
359 TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1),
360 TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1),
361 TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1,
362 1),
363 TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux",
364 CK_TOP_PEXTP_TL, 1, 1),
365 TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1),
366 TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
367};
368
369/* INFRASYS MUX PARENTS */
370static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART };
371
372static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 };
373
374static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 };
375
376static const int infra_pwm1_parents[] = { -1, -1, -1, CK_INFRA_PWM };
377
378static const int infra_pwm_bsel_parents[] = { -1, -1, -1, CK_INFRA_PWM };
379
380static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M,
381 CK_TOP_CB_CKSQ_40M, CK_INFRA_PCIE_CK};
382
383#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
384 { \
385 .id = _id, .mux_reg = (_reg) + 0x8, \
386 .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
387 .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
388 .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \
389 .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
390 }
391
392/* INFRA MUX */
393static const struct mtk_composite infra_muxes[] = {
394 INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
395 0x10, 0, 1),
396 INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
397 0x10, 1, 1),
398 INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
399 0x10, 2, 1),
400 INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
401 4, 1),
402 INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
403 5, 1),
404 INFRA_MUX(CK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10,
405 6, 1),
406 INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10,
407 9, 2),
408 INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10,
409 11, 2),
410 INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
411 0x10, 13, 2),
412 INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
413 0, 2),
414};
415
416static const struct mtk_gate_regs infra_0_cg_regs = {
417 .set_ofs = 0x40,
418 .clr_ofs = 0x44,
419 .sta_ofs = 0x48,
420};
421
422static const struct mtk_gate_regs infra_1_cg_regs = {
423 .set_ofs = 0x50,
424 .clr_ofs = 0x54,
425 .sta_ofs = 0x58,
426};
427
428static const struct mtk_gate_regs infra_2_cg_regs = {
429 .set_ofs = 0x60,
430 .clr_ofs = 0x64,
431 .sta_ofs = 0x68,
432};
433
434#define GATE_INFRA0(_id, _name, _parent, _shift) \
435 { \
436 .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
437 .shift = _shift, \
438 .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
439 }
440
441#define GATE_INFRA1(_id, _name, _parent, _shift) \
442 { \
443 .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
444 .shift = _shift, \
445 .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
446 }
447
448#define GATE_INFRA2(_id, _name, _parent, _shift) \
449 { \
450 .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
451 .shift = _shift, \
452 .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
453 }
454
455/* INFRA GATE */
456static const struct mtk_gate infracfg_ao_gates[] = {
457 GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0),
458 GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1),
459 GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2),
460 GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3),
461 GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4),
462 GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6),
463 GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8),
464 GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9),
465 GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10),
466 GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK,
467 11),
468 GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK,
469 13),
470 GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M,
471 14),
472 GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15),
473 GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16),
474 GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24),
475 GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25),
476 GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0),
477 GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1),
478 GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2),
479 GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3),
480 GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4),
481 GATE_INFRA1(CK_INFRA_SPI2_CK, "infra_spi2", CK_INFRA_MUX_SPI2, 6),
482 GATE_INFRA1(CK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CK_INFRA_66M_MCK,
483 7),
484 GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8),
485 GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK,
486 9),
487 GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10),
488 GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11),
489 GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12),
490 GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK,
491 13),
492 GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK,
493 14),
494 GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15),
495 GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16),
496 GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
497 CK_INFRA_FMSDC_HCK_CK, 17),
498 GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
499 CK_INFRA_PERI_133M, 18),
500 GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK,
501 19),
502 GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_TOP_F26M, 20),
503 GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_TOP_F26M, 21),
504 GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK,
505 23),
506 GATE_INFRA1(CK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CK_INFRA_133M_MCK,
507 25),
508 GATE_INFRA1(CK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CK_INFRA_66M_MCK, 26),
509 GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK,
510 0),
511 GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK,
512 1),
513 GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK,
514 2),
515 GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3),
516 GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie",
517 CK_INFRA_PCIE_GFMUX_TL_O_PRE, 12),
518 GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 14),
519 GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15),
520};
521
522static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = {
523 .fdivs_offs = CLK_APMIXED_NR_CLK,
524 .xtal_rate = 40 * MHZ,
525 .fclks = fixed_pll_clks,
526};
527
528static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
529 .fdivs_offs = CK_TOP_CB_M_416M,
530 .muxes_offs = CK_TOP_NFI1X_SEL,
531 .fclks = top_fixed_clks,
532 .fdivs = top_fixed_divs,
533 .muxes = top_muxes,
534 .flags = CLK_BYPASS_XTAL,
535};
536
537static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
538 .fdivs_offs = CK_INFRA_CK_F26M,
539 .muxes_offs = CK_INFRA_UART0_SEL,
540 .fdivs = infra_fixed_divs,
541 .muxes = infra_muxes,
542};
543
544static const struct udevice_id mt7981_fixed_pll_compat[] = {
545 { .compatible = "mediatek,mt7981-fixed-plls" },
546 {}
547};
548
549static const struct udevice_id mt7981_topckgen_compat[] = {
550 { .compatible = "mediatek,mt7981-topckgen" },
551 {}
552};
553
554static int mt7981_fixed_pll_probe(struct udevice *dev)
555{
556 return mtk_common_clk_init(dev, &mt7981_fixed_pll_clk_tree);
557}
558
559static int mt7981_topckgen_probe(struct udevice *dev)
560{
561 struct mtk_clk_priv *priv = dev_get_priv(dev);
562
563 priv->base = dev_read_addr_ptr(dev);
564 writel(MT7981_CLK_PDN_EN_WRITE, priv->base + MT7981_CLK_PDN);
565
566 return mtk_common_clk_init(dev, &mt7981_topckgen_clk_tree);
567}
568
569U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
570 .name = "mt7981-clock-fixed-pll",
571 .id = UCLASS_CLK,
572 .of_match = mt7981_fixed_pll_compat,
573 .probe = mt7981_fixed_pll_probe,
574 .priv_auto = sizeof(struct mtk_clk_priv),
575 .ops = &mtk_clk_topckgen_ops,
576 .flags = DM_FLAG_PRE_RELOC,
577};
578
579U_BOOT_DRIVER(mtk_clk_topckgen) = {
580 .name = "mt7981-clock-topckgen",
581 .id = UCLASS_CLK,
582 .of_match = mt7981_topckgen_compat,
583 .probe = mt7981_topckgen_probe,
584 .priv_auto = sizeof(struct mtk_clk_priv),
585 .ops = &mtk_clk_topckgen_ops,
586 .flags = DM_FLAG_PRE_RELOC,
587};
588
589static const struct udevice_id mt7981_infracfg_compat[] = {
590 { .compatible = "mediatek,mt7981-infracfg" },
591 {}
592};
593
594static const struct udevice_id mt7981_infracfg_ao_compat[] = {
595 { .compatible = "mediatek,mt7981-infracfg_ao" },
596 {}
597};
598
599static int mt7981_infracfg_probe(struct udevice *dev)
600{
601 return mtk_common_clk_init(dev, &mt7981_infracfg_clk_tree);
602}
603
604static int mt7981_infracfg_ao_probe(struct udevice *dev)
605{
606 return mtk_common_clk_gate_init(dev, &mt7981_infracfg_clk_tree,
607 infracfg_ao_gates);
608}
609
610U_BOOT_DRIVER(mtk_clk_infracfg) = {
611 .name = "mt7981-clock-infracfg",
612 .id = UCLASS_CLK,
613 .of_match = mt7981_infracfg_compat,
614 .probe = mt7981_infracfg_probe,
615 .priv_auto = sizeof(struct mtk_clk_priv),
616 .ops = &mtk_clk_infrasys_ops,
617 .flags = DM_FLAG_PRE_RELOC,
618};
619
620U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
621 .name = "mt7981-clock-infracfg-ao",
622 .id = UCLASS_CLK,
623 .of_match = mt7981_infracfg_ao_compat,
624 .probe = mt7981_infracfg_ao_probe,
625 .priv_auto = sizeof(struct mtk_cg_priv),
626 .ops = &mtk_clk_gate_ops,
627 .flags = DM_FLAG_PRE_RELOC,
628};
629
630/* ethsys */
631static const struct mtk_gate_regs eth_cg_regs = {
632 .set_ofs = 0x30,
633 .clr_ofs = 0x30,
634 .sta_ofs = 0x30,
635};
636
637#define GATE_ETH(_id, _name, _parent, _shift) \
638 { \
639 .id = _id, .parent = _parent, .regs = &eth_cg_regs, \
640 .shift = _shift, \
641 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
642 }
643
644static const struct mtk_gate eth_cgs[] = {
645 GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 6),
646 GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 7),
647 GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8),
648 GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15),
649};
650
651static int mt7981_ethsys_probe(struct udevice *dev)
652{
653 return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,
654 eth_cgs);
655}
656
657static int mt7981_ethsys_bind(struct udevice *dev)
658{
659 int ret = 0;
660
661 if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
662 ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
663 if (ret)
664 debug("Warning: failed to bind reset controller\n");
665 }
666
667 return ret;
668}
669
670static const struct udevice_id mt7981_ethsys_compat[] = {
671 { .compatible = "mediatek,mt7981-ethsys", },
672 {}
673};
674
675U_BOOT_DRIVER(mtk_clk_ethsys) = {
676 .name = "mt7981-clock-ethsys",
677 .id = UCLASS_CLK,
678 .of_match = mt7981_ethsys_compat,
679 .probe = mt7981_ethsys_probe,
680 .bind = mt7981_ethsys_bind,
681 .priv_auto = sizeof(struct mtk_cg_priv),
682 .ops = &mtk_clk_gate_ops,
683};