dts/upstream/Bindings/timer/arm,sp804.yaml

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/arm,sp804.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM sp804 Dual Timers

maintainers:
  - Haojian Zhuang <haojian.zhuang@linaro.org>

description: |+
  The Arm SP804 IP implements two independent timers, configurable for
  16 or 32 bit operation and capable of running in one-shot, periodic, or
  free-running mode. The input clock is shared, but can be gated and prescaled
  independently for each timer.

  There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
  SoCs, such as Hi1212, should use the dedicated compatible: "hisilicon,sp804".

# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
  properties:
    compatible:
      contains:
        enum:
          - arm,sp804
          - hisilicon,sp804
  required:
    - compatible

properties:
  compatible:
    items:
      - enum:
          - arm,sp804
          - hisilicon,sp804
      - const: arm,primecell

  interrupts:
    description: |
      If two interrupts are listed, those are the interrupts for timer
      1 and 2, respectively. If there is only a single interrupt, it is
      either a combined interrupt or the sole interrupt of one timer, as
      specified by the "arm,sp804-has-irq" property.
    minItems: 1
    maxItems: 2

  reg:
    description: The physical base address of the SP804 IP.
    maxItems: 1

  clocks:
    description: |
      Clocks driving the dual timer hardware. This list should
      be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1
      clock, apb_pclk. A single clock can also be specified if the same
      clock is used for all clock inputs.
    oneOf:
      - items:
          - description: clock for timer 1
          - description: clock for timer 2
          - description: bus clock
      - items:
          - description: unified clock for both timers and the bus

  clock-names: true
    # The original binding did not specify any clock names, and there is no
    # consistent naming used in the existing DTs. The primecell binding
    # requires the "apb_pclk" name, so we need this property.
    # Use "timer0clk", "timer1clk", "apb_pclk" for new DTs.

  arm,sp804-has-irq:
    description: If only one interrupt line is connected to the interrupt
      controller, this property specifies which timer is connected to this
      line.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 2

required:
  - compatible
  - interrupts
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    timer0: timer@fc800000 {
        compatible = "arm,sp804", "arm,primecell";
        reg = <0xfc800000 0x1000>;
        interrupts = <0 0 4>, <0 1 4>;
        clocks = <&timclk1>, <&timclk2>, <&pclk>;
        clock-names = "timer1", "timer2", "apb_pclk";
    };