| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (c) 2018 Bitmain Ltd. |
| 4 | * Copyright (c) 2019 Linaro Ltd. |
| 5 | */ |
| 6 | |
| 7 | #ifndef _DT_BINDINGS_BM1880_RESET_H |
| 8 | #define _DT_BINDINGS_BM1880_RESET_H |
| 9 | |
| 10 | #define BM1880_RST_MAIN_AP 0 |
| 11 | #define BM1880_RST_SECOND_AP 1 |
| 12 | #define BM1880_RST_DDR 2 |
| 13 | #define BM1880_RST_VIDEO 3 |
| 14 | #define BM1880_RST_JPEG 4 |
| 15 | #define BM1880_RST_VPP 5 |
| 16 | #define BM1880_RST_GDMA 6 |
| 17 | #define BM1880_RST_AXI_SRAM 7 |
| 18 | #define BM1880_RST_TPU 8 |
| 19 | #define BM1880_RST_USB 9 |
| 20 | #define BM1880_RST_ETH0 10 |
| 21 | #define BM1880_RST_ETH1 11 |
| 22 | #define BM1880_RST_NAND 12 |
| 23 | #define BM1880_RST_EMMC 13 |
| 24 | #define BM1880_RST_SD 14 |
| 25 | #define BM1880_RST_SDMA 15 |
| 26 | #define BM1880_RST_I2S0 16 |
| 27 | #define BM1880_RST_I2S1 17 |
| 28 | #define BM1880_RST_UART0_1_CLK 18 |
| 29 | #define BM1880_RST_UART0_1_ACLK 19 |
| 30 | #define BM1880_RST_UART2_3_CLK 20 |
| 31 | #define BM1880_RST_UART2_3_ACLK 21 |
| 32 | #define BM1880_RST_MINER 22 |
| 33 | #define BM1880_RST_I2C0 23 |
| 34 | #define BM1880_RST_I2C1 24 |
| 35 | #define BM1880_RST_I2C2 25 |
| 36 | #define BM1880_RST_I2C3 26 |
| 37 | #define BM1880_RST_I2C4 27 |
| 38 | #define BM1880_RST_PWM0 28 |
| 39 | #define BM1880_RST_PWM1 29 |
| 40 | #define BM1880_RST_PWM2 30 |
| 41 | #define BM1880_RST_PWM3 31 |
| 42 | #define BM1880_RST_SPI 32 |
| 43 | #define BM1880_RST_GPIO0 33 |
| 44 | #define BM1880_RST_GPIO1 34 |
| 45 | #define BM1880_RST_GPIO2 35 |
| 46 | #define BM1880_RST_EFUSE 36 |
| 47 | #define BM1880_RST_WDT 37 |
| 48 | #define BM1880_RST_AHB_ROM 38 |
| 49 | #define BM1880_RST_SPIC 39 |
| 50 | |
| 51 | #endif /* _DT_BINDINGS_BM1880_RESET_H */ |