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git01.mediatek.com / filogic / uboot / 668ad57698edbd733de3760cf0ea4f438ab04aeb / . / dts / upstream / include / dt-bindings / clock / qcom,sm8550-camcc.h
blob: a2a256691c2bdd4a355f7592511a79abe9eaed45 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2/*
3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H
7#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H
8
9/* CAM_CC clocks */
10#define CAM_CC_BPS_AHB_CLK 0
11#define CAM_CC_BPS_CLK 1
12#define CAM_CC_BPS_CLK_SRC 2
13#define CAM_CC_BPS_FAST_AHB_CLK 3
14#define CAM_CC_CAMNOC_AXI_CLK 4
15#define CAM_CC_CAMNOC_AXI_CLK_SRC 5
16#define CAM_CC_CAMNOC_DCD_XO_CLK 6
17#define CAM_CC_CAMNOC_XO_CLK 7
18#define CAM_CC_CCI_0_CLK 8
19#define CAM_CC_CCI_0_CLK_SRC 9
20#define CAM_CC_CCI_1_CLK 10
21#define CAM_CC_CCI_1_CLK_SRC 11
22#define CAM_CC_CCI_2_CLK 12
23#define CAM_CC_CCI_2_CLK_SRC 13
24#define CAM_CC_CORE_AHB_CLK 14
25#define CAM_CC_CPAS_AHB_CLK 15
26#define CAM_CC_CPAS_BPS_CLK 16
27#define CAM_CC_CPAS_CRE_CLK 17
28#define CAM_CC_CPAS_FAST_AHB_CLK 18
29#define CAM_CC_CPAS_IFE_0_CLK 19
30#define CAM_CC_CPAS_IFE_1_CLK 20
31#define CAM_CC_CPAS_IFE_2_CLK 21
32#define CAM_CC_CPAS_IFE_LITE_CLK 22
33#define CAM_CC_CPAS_IPE_NPS_CLK 23
34#define CAM_CC_CPAS_SBI_CLK 24
35#define CAM_CC_CPAS_SFE_0_CLK 25
36#define CAM_CC_CPAS_SFE_1_CLK 26
37#define CAM_CC_CPHY_RX_CLK_SRC 27
38#define CAM_CC_CRE_AHB_CLK 28
39#define CAM_CC_CRE_CLK 29
40#define CAM_CC_CRE_CLK_SRC 30
41#define CAM_CC_CSI0PHYTIMER_CLK 31
42#define CAM_CC_CSI0PHYTIMER_CLK_SRC 32
43#define CAM_CC_CSI1PHYTIMER_CLK 33
44#define CAM_CC_CSI1PHYTIMER_CLK_SRC 34
45#define CAM_CC_CSI2PHYTIMER_CLK 35
46#define CAM_CC_CSI2PHYTIMER_CLK_SRC 36
47#define CAM_CC_CSI3PHYTIMER_CLK 37
48#define CAM_CC_CSI3PHYTIMER_CLK_SRC 38
49#define CAM_CC_CSI4PHYTIMER_CLK 39
50#define CAM_CC_CSI4PHYTIMER_CLK_SRC 40
51#define CAM_CC_CSI5PHYTIMER_CLK 41
52#define CAM_CC_CSI5PHYTIMER_CLK_SRC 42
53#define CAM_CC_CSI6PHYTIMER_CLK 43
54#define CAM_CC_CSI6PHYTIMER_CLK_SRC 44
55#define CAM_CC_CSI7PHYTIMER_CLK 45
56#define CAM_CC_CSI7PHYTIMER_CLK_SRC 46
57#define CAM_CC_CSID_CLK 47
58#define CAM_CC_CSID_CLK_SRC 48
59#define CAM_CC_CSID_CSIPHY_RX_CLK 49
60#define CAM_CC_CSIPHY0_CLK 50
61#define CAM_CC_CSIPHY1_CLK 51
62#define CAM_CC_CSIPHY2_CLK 52
63#define CAM_CC_CSIPHY3_CLK 53
64#define CAM_CC_CSIPHY4_CLK 54
65#define CAM_CC_CSIPHY5_CLK 55
66#define CAM_CC_CSIPHY6_CLK 56
67#define CAM_CC_CSIPHY7_CLK 57
68#define CAM_CC_DRV_AHB_CLK 58
69#define CAM_CC_DRV_XO_CLK 59
70#define CAM_CC_FAST_AHB_CLK_SRC 60
71#define CAM_CC_GDSC_CLK 61
72#define CAM_CC_ICP_AHB_CLK 62
73#define CAM_CC_ICP_CLK 63
74#define CAM_CC_ICP_CLK_SRC 64
75#define CAM_CC_IFE_0_CLK 65
76#define CAM_CC_IFE_0_CLK_SRC 66
77#define CAM_CC_IFE_0_DSP_CLK 67
78#define CAM_CC_IFE_0_DSP_CLK_SRC 68
79#define CAM_CC_IFE_0_FAST_AHB_CLK 69
80#define CAM_CC_IFE_1_CLK 70
81#define CAM_CC_IFE_1_CLK_SRC 71
82#define CAM_CC_IFE_1_DSP_CLK 72
83#define CAM_CC_IFE_1_DSP_CLK_SRC 73
84#define CAM_CC_IFE_1_FAST_AHB_CLK 74
85#define CAM_CC_IFE_2_CLK 75
86#define CAM_CC_IFE_2_CLK_SRC 76
87#define CAM_CC_IFE_2_DSP_CLK 77
88#define CAM_CC_IFE_2_DSP_CLK_SRC 78
89#define CAM_CC_IFE_2_FAST_AHB_CLK 79
90#define CAM_CC_IFE_LITE_AHB_CLK 80
91#define CAM_CC_IFE_LITE_CLK 81
92#define CAM_CC_IFE_LITE_CLK_SRC 82
93#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83
94#define CAM_CC_IFE_LITE_CSID_CLK 84
95#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85
96#define CAM_CC_IPE_NPS_AHB_CLK 86
97#define CAM_CC_IPE_NPS_CLK 87
98#define CAM_CC_IPE_NPS_CLK_SRC 88
99#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89
100#define CAM_CC_IPE_PPS_CLK 90
101#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91
102#define CAM_CC_JPEG_1_CLK 92
103#define CAM_CC_JPEG_CLK 93
104#define CAM_CC_JPEG_CLK_SRC 94
105#define CAM_CC_MCLK0_CLK 95
106#define CAM_CC_MCLK0_CLK_SRC 96
107#define CAM_CC_MCLK1_CLK 97
108#define CAM_CC_MCLK1_CLK_SRC 98
109#define CAM_CC_MCLK2_CLK 99
110#define CAM_CC_MCLK2_CLK_SRC 100
111#define CAM_CC_MCLK3_CLK 101
112#define CAM_CC_MCLK3_CLK_SRC 102
113#define CAM_CC_MCLK4_CLK 103
114#define CAM_CC_MCLK4_CLK_SRC 104
115#define CAM_CC_MCLK5_CLK 105
116#define CAM_CC_MCLK5_CLK_SRC 106
117#define CAM_CC_MCLK6_CLK 107
118#define CAM_CC_MCLK6_CLK_SRC 108
119#define CAM_CC_MCLK7_CLK 109
120#define CAM_CC_MCLK7_CLK_SRC 110
121#define CAM_CC_PLL0 111
122#define CAM_CC_PLL0_OUT_EVEN 112
123#define CAM_CC_PLL0_OUT_ODD 113
124#define CAM_CC_PLL1 114
125#define CAM_CC_PLL1_OUT_EVEN 115
126#define CAM_CC_PLL2 116
127#define CAM_CC_PLL3 117
128#define CAM_CC_PLL3_OUT_EVEN 118
129#define CAM_CC_PLL4 119
130#define CAM_CC_PLL4_OUT_EVEN 120
131#define CAM_CC_PLL5 121
132#define CAM_CC_PLL5_OUT_EVEN 122
133#define CAM_CC_PLL6 123
134#define CAM_CC_PLL6_OUT_EVEN 124
135#define CAM_CC_PLL7 125
136#define CAM_CC_PLL7_OUT_EVEN 126
137#define CAM_CC_PLL8 127
138#define CAM_CC_PLL8_OUT_EVEN 128
139#define CAM_CC_PLL9 129
140#define CAM_CC_PLL9_OUT_EVEN 130
141#define CAM_CC_PLL10 131
142#define CAM_CC_PLL10_OUT_EVEN 132
143#define CAM_CC_PLL11 133
144#define CAM_CC_PLL11_OUT_EVEN 134
145#define CAM_CC_PLL12 135
146#define CAM_CC_PLL12_OUT_EVEN 136
147#define CAM_CC_QDSS_DEBUG_CLK 137
148#define CAM_CC_QDSS_DEBUG_CLK_SRC 138
149#define CAM_CC_QDSS_DEBUG_XO_CLK 139
150#define CAM_CC_SBI_CLK 140
151#define CAM_CC_SBI_FAST_AHB_CLK 141
152#define CAM_CC_SFE_0_CLK 142
153#define CAM_CC_SFE_0_CLK_SRC 143
154#define CAM_CC_SFE_0_FAST_AHB_CLK 144
155#define CAM_CC_SFE_1_CLK 145
156#define CAM_CC_SFE_1_CLK_SRC 146
157#define CAM_CC_SFE_1_FAST_AHB_CLK 147
158#define CAM_CC_SLEEP_CLK 148
159#define CAM_CC_SLEEP_CLK_SRC 149
160#define CAM_CC_SLOW_AHB_CLK_SRC 150
161#define CAM_CC_XO_CLK_SRC 151
162
163/* CAM_CC power domains */
164#define CAM_CC_BPS_GDSC 0
165#define CAM_CC_IFE_0_GDSC 1
166#define CAM_CC_IFE_1_GDSC 2
167#define CAM_CC_IFE_2_GDSC 3
168#define CAM_CC_IPE_0_GDSC 4
169#define CAM_CC_SBI_GDSC 5
170#define CAM_CC_SFE_0_GDSC 6
171#define CAM_CC_SFE_1_GDSC 7
172#define CAM_CC_TITAN_TOP_GDSC 8
173
174/* CAM_CC resets */
175#define CAM_CC_BPS_BCR 0
176#define CAM_CC_DRV_BCR 1
177#define CAM_CC_ICP_BCR 2
178#define CAM_CC_IFE_0_BCR 3
179#define CAM_CC_IFE_1_BCR 4
180#define CAM_CC_IFE_2_BCR 5
181#define CAM_CC_IPE_0_BCR 6
182#define CAM_CC_QDSS_DEBUG_BCR 7
183#define CAM_CC_SBI_BCR 8
184#define CAM_CC_SFE_0_BCR 9
185#define CAM_CC_SFE_1_BCR 10
186
187#endif