| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Texas Instruments K3 Interrupt Router |
| 8 | |
| 9 | maintainers: |
| 10 | - Lokesh Vutla <lokeshvutla@ti.com> |
| 11 | |
| 12 | allOf: |
| 13 | - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# |
| 14 | |
| 15 | description: | |
| 16 | The Interrupt Router (INTR) module provides a mechanism to mux M |
| 17 | interrupt inputs to N interrupt outputs, where all M inputs are selectable |
| 18 | to be driven per N output. An Interrupt Router can either handle edge |
| 19 | triggered or level triggered interrupts and that is fixed in hardware. |
| 20 | |
| 21 | Interrupt Router |
| 22 | +----------------------+ |
| 23 | | Inputs Outputs | |
| 24 | +-------+ | +------+ +-----+ | |
| 25 | | GPIO |----------->| | irq0 | | 0 | | Host IRQ |
| 26 | +-------+ | +------+ +-----+ | controller |
| 27 | | . . | +-------+ |
| 28 | +-------+ | . . |----->| IRQ | |
| 29 | | INTA |----------->| . . | +-------+ |
| 30 | +-------+ | . +-----+ | |
| 31 | | +------+ | N | | |
| 32 | | | irqM | +-----+ | |
| 33 | | +------+ | |
| 34 | | | |
| 35 | +----------------------+ |
| 36 | |
| 37 | There is one register per output (MUXCNTL_N) that controls the selection. |
| 38 | Configuration of these MUXCNTL_N registers is done by a system controller |
| 39 | (like the Device Memory and Security Controller on K3 AM654 SoC). System |
| 40 | controller will keep track of the used and unused registers within the Router. |
| 41 | Driver should request the system controller to get the range of GIC IRQs |
| 42 | assigned to the requesting hosts. It is the drivers responsibility to keep |
| 43 | track of Host IRQs. |
| 44 | |
| 45 | Communication between the host processor running an OS and the system |
| 46 | controller happens through a protocol called TI System Control Interface |
| 47 | (TISCI protocol). |
| 48 | |
| 49 | properties: |
| 50 | compatible: |
| 51 | const: ti,sci-intr |
| 52 | |
| 53 | ti,intr-trigger-type: |
| 54 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 55 | enum: [1, 4] |
| 56 | description: | |
| 57 | Should be one of the following. |
| 58 | 1 = If intr supports edge triggered interrupts. |
| 59 | 4 = If intr supports level triggered interrupts. |
| 60 | |
| 61 | reg: |
| 62 | maxItems: 1 |
| 63 | |
| 64 | interrupt-controller: true |
| 65 | |
| 66 | '#interrupt-cells': |
| 67 | const: 1 |
| 68 | description: | |
| 69 | The 1st cell should contain interrupt router input hw number. |
| 70 | |
| 71 | ti,interrupt-ranges: |
| 72 | $ref: /schemas/types.yaml#/definitions/uint32-matrix |
| 73 | description: | |
| 74 | Interrupt ranges that converts the INTR output hw irq numbers |
| 75 | to parents's input interrupt numbers. |
| 76 | items: |
| 77 | items: |
| 78 | - description: | |
| 79 | "output_irq" specifies the base for intr output irq |
| 80 | - description: | |
| 81 | "parent's input irq" specifies the base for parent irq |
| 82 | - description: | |
| 83 | "limit" specifies the limit for translation |
| 84 | |
| 85 | required: |
| 86 | - compatible |
| 87 | - ti,intr-trigger-type |
| 88 | - interrupt-controller |
| 89 | - '#interrupt-cells' |
| 90 | - ti,sci |
| 91 | - ti,sci-dev-id |
| 92 | - ti,interrupt-ranges |
| 93 | |
| 94 | unevaluatedProperties: false |
| 95 | |
| 96 | examples: |
| 97 | - | |
| 98 | main_gpio_intr: interrupt-controller0 { |
| 99 | compatible = "ti,sci-intr"; |
| 100 | ti,intr-trigger-type = <1>; |
| 101 | interrupt-controller; |
| 102 | interrupt-parent = <&gic500>; |
| 103 | #interrupt-cells = <1>; |
| 104 | ti,sci = <&dmsc>; |
| 105 | ti,sci-dev-id = <131>; |
| 106 | ti,interrupt-ranges = <0 360 32>; |
| 107 | }; |