Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | * Freescale Layerscape SCFG PCIe MSI controller |
| 2 | |
| 3 | Required properties: |
| 4 | |
| 5 | - compatible: should be "fsl,<soc-name>-msi" to identify |
| 6 | Layerscape PCIe MSI controller block such as: |
| 7 | "fsl,ls1021a-msi" |
| 8 | "fsl,ls1043a-msi" |
| 9 | "fsl,ls1046a-msi" |
| 10 | "fsl,ls1043a-v1.1-msi" |
| 11 | "fsl,ls1012a-msi" |
| 12 | - msi-controller: indicates that this is a PCIe MSI controller node |
| 13 | - reg: physical base address of the controller and length of memory mapped. |
| 14 | - interrupts: an interrupt to the parent interrupt controller. |
| 15 | |
| 16 | This interrupt controller hardware is a second level interrupt controller that |
| 17 | is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based |
| 18 | platforms. If interrupt-parent is not provided, the default parent interrupt |
| 19 | controller will be used. |
| 20 | Each PCIe node needs to have property msi-parent that points to |
| 21 | MSI controller node |
| 22 | |
| 23 | Examples: |
| 24 | |
| 25 | msi1: msi-controller@1571000 { |
| 26 | compatible = "fsl,ls1043a-msi"; |
| 27 | reg = <0x0 0x1571000 0x0 0x8>, |
| 28 | msi-controller; |
| 29 | interrupts = <0 116 0x4>; |
| 30 | }; |