| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-hcu.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Intel Keem Bay OCS HCU |
| 8 | |
| 9 | maintainers: |
| 10 | - Declan Murphy <declan.murphy@intel.com> |
| 11 | - Daniele Alessandrelli <daniele.alessandrelli@intel.com> |
| 12 | |
| 13 | description: |
| 14 | The Intel Keem Bay Offload and Crypto Subsystem (OCS) Hash Control Unit (HCU) |
| 15 | provides hardware-accelerated hashing and HMAC. |
| 16 | |
| 17 | properties: |
| 18 | compatible: |
| 19 | const: intel,keembay-ocs-hcu |
| 20 | |
| 21 | reg: |
| 22 | maxItems: 1 |
| 23 | |
| 24 | interrupts: |
| 25 | maxItems: 1 |
| 26 | |
| 27 | clocks: |
| 28 | maxItems: 1 |
| 29 | |
| 30 | required: |
| 31 | - compatible |
| 32 | - reg |
| 33 | - interrupts |
| 34 | - clocks |
| 35 | |
| 36 | additionalProperties: false |
| 37 | |
| 38 | examples: |
| 39 | - | |
| 40 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 41 | crypto@3000b000 { |
| 42 | compatible = "intel,keembay-ocs-hcu"; |
| 43 | reg = <0x3000b000 0x1000>; |
| 44 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| 45 | clocks = <&scmi_clk 94>; |
| 46 | }; |