Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | Device tree bindings for i.MX Wireless External Interface Module (WEIM) |
| 2 | |
| 3 | The term "wireless" does not imply that the WEIM is literally an interface |
| 4 | without wires. It simply means that this module was originally designed for |
| 5 | wireless and mobile applications that use low-power technology. |
| 6 | |
| 7 | The actual devices are instantiated from the child nodes of a WEIM node. |
| 8 | |
| 9 | Required properties: |
| 10 | |
| 11 | - compatible: Should contain one of the following: |
| 12 | "fsl,imx1-weim" |
| 13 | "fsl,imx27-weim" |
| 14 | "fsl,imx51-weim" |
| 15 | "fsl,imx50-weim" |
| 16 | "fsl,imx6q-weim" |
| 17 | - reg: A resource specifier for the register space |
| 18 | (see the example below) |
| 19 | - clocks: the clock, see the example below. |
| 20 | - #address-cells: Must be set to 2 to allow memory address translation |
| 21 | - #size-cells: Must be set to 1 to allow CS address passing |
| 22 | - ranges: Must be set up to reflect the memory layout with four |
| 23 | integer values for each chip-select line in use: |
| 24 | |
| 25 | <cs-number> 0 <physical address of mapping> <size> |
| 26 | |
| 27 | Optional properties: |
| 28 | |
| 29 | - fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of |
| 30 | devices, it should be the phandle to the system General |
| 31 | Purpose Register controller that contains WEIM CS GPR |
| 32 | register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0] |
| 33 | should be set up as one of the following 4 possible |
| 34 | values depending on the CS space configuration. |
| 35 | |
| 36 | IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3 |
| 37 | --------------------------------------------- |
| 38 | 05 128M 0M 0M 0M |
| 39 | 033 64M 64M 0M 0M |
| 40 | 0113 64M 32M 32M 0M |
| 41 | 01111 32M 32M 32M 32M |
| 42 | |
| 43 | In case that the property is absent, the reset value or |
| 44 | what bootloader sets up in IOMUXC_GPR1[11:0] will be |
| 45 | used. |
| 46 | |
| 47 | - fsl,burst-clk-enable For "fsl,imx50-weim" and "fsl,imx6q-weim" type of |
| 48 | devices, the presence of this property indicates that |
| 49 | the weim bus should operate in Burst Clock Mode. |
| 50 | |
| 51 | - fsl,continuous-burst-clk Make Burst Clock to output continuous clock. |
| 52 | Without this option Burst Clock will output clock |
| 53 | only when necessary. This takes effect only if |
| 54 | "fsl,burst-clk-enable" is set. |
| 55 | |
| 56 | Timing property for child nodes. It is mandatory, not optional. |
| 57 | |
| 58 | - fsl,weim-cs-timing: The timing array, contains timing values for the |
| 59 | child node. We get the CS indexes from the address |
| 60 | ranges in the child node's "reg" property. |
| 61 | The number of registers depends on the selected chip: |
| 62 | For i.MX1, i.MX21 ("fsl,imx1-weim") there are two |
| 63 | registers: CSxU, CSxL. |
| 64 | For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim") |
| 65 | there are three registers: CSCRxU, CSCRxL, CSCRxA. |
| 66 | For i.MX50, i.MX53 ("fsl,imx50-weim"), |
| 67 | i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim") |
| 68 | there are six registers: CSxGCR1, CSxGCR2, CSxRCR1, |
| 69 | CSxRCR2, CSxWCR1, CSxWCR2. |
| 70 | |
| 71 | Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM: |
| 72 | |
| 73 | weim: weim@21b8000 { |
| 74 | compatible = "fsl,imx6q-weim"; |
| 75 | reg = <0x021b8000 0x4000>; |
| 76 | clocks = <&clks 196>; |
| 77 | #address-cells = <2>; |
| 78 | #size-cells = <1>; |
| 79 | ranges = <0 0 0x08000000 0x08000000>; |
| 80 | fsl,weim-cs-gpr = <&gpr>; |
| 81 | |
| 82 | nor@0,0 { |
| 83 | compatible = "cfi-flash"; |
| 84 | reg = <0 0 0x02000000>; |
| 85 | #address-cells = <1>; |
| 86 | #size-cells = <1>; |
| 87 | bank-width = <2>; |
| 88 | fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 |
| 89 | 0x0000c000 0x1404a38e 0x00000000>; |
| 90 | }; |
| 91 | }; |
| 92 | |
| 93 | Example for an imx6q-based board, a multi-chipselect device connected to WEIM: |
| 94 | |
| 95 | In this case, both chip select 0 and 1 will be configured with the same timing |
| 96 | array values. |
| 97 | |
| 98 | weim: weim@21b8000 { |
| 99 | compatible = "fsl,imx6q-weim"; |
| 100 | reg = <0x021b8000 0x4000>; |
| 101 | clocks = <&clks 196>; |
| 102 | #address-cells = <2>; |
| 103 | #size-cells = <1>; |
| 104 | ranges = <0 0 0x08000000 0x02000000 |
| 105 | 1 0 0x0a000000 0x02000000 |
| 106 | 2 0 0x0c000000 0x02000000 |
| 107 | 3 0 0x0e000000 0x02000000>; |
| 108 | fsl,weim-cs-gpr = <&gpr>; |
| 109 | |
| 110 | acme@0 { |
| 111 | compatible = "acme,whatever"; |
| 112 | reg = <0 0 0x100>, <0 0x400000 0x800>, |
| 113 | <1 0x400000 0x800>; |
| 114 | fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100 |
| 115 | 0x00000000 0xa0000240 0x00000000>; |
| 116 | }; |
| 117 | }; |