| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Synopsys DWC AHCI SATA controller for Rockchip devices |
| 8 | |
| 9 | maintainers: |
| 10 | - Serge Semin <fancer.lancer@gmail.com> |
| 11 | |
| 12 | description: |
| 13 | This document defines device tree bindings for the Synopsys DWC |
| 14 | implementation of the AHCI SATA controller found in Rockchip |
| 15 | devices. |
| 16 | |
| 17 | select: |
| 18 | properties: |
| 19 | compatible: |
| 20 | contains: |
| 21 | enum: |
| 22 | - rockchip,rk3568-dwc-ahci |
| 23 | - rockchip,rk3588-dwc-ahci |
| 24 | required: |
| 25 | - compatible |
| 26 | |
| 27 | properties: |
| 28 | compatible: |
| 29 | items: |
| 30 | - enum: |
| 31 | - rockchip,rk3568-dwc-ahci |
| 32 | - rockchip,rk3588-dwc-ahci |
| 33 | - const: snps,dwc-ahci |
| 34 | |
| 35 | ports-implemented: |
| 36 | const: 1 |
| 37 | |
| 38 | sata-port@0: |
| 39 | $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port |
| 40 | |
| 41 | properties: |
| 42 | reg: |
| 43 | const: 0 |
| 44 | |
| 45 | unevaluatedProperties: false |
| 46 | |
| 47 | patternProperties: |
| 48 | "^sata-port@[1-9a-e]$": false |
| 49 | |
| 50 | required: |
| 51 | - compatible |
| 52 | - reg |
| 53 | - interrupts |
| 54 | - clocks |
| 55 | - clock-names |
| 56 | - ports-implemented |
| 57 | |
| 58 | allOf: |
| 59 | - $ref: snps,dwc-ahci-common.yaml# |
| 60 | - if: |
| 61 | properties: |
| 62 | compatible: |
| 63 | contains: |
| 64 | enum: |
| 65 | - rockchip,rk3588-dwc-ahci |
| 66 | then: |
| 67 | properties: |
| 68 | clocks: |
| 69 | maxItems: 5 |
| 70 | clock-names: |
| 71 | items: |
| 72 | - const: sata |
| 73 | - const: pmalive |
| 74 | - const: rxoob |
| 75 | - const: ref |
| 76 | - const: asic |
| 77 | - if: |
| 78 | properties: |
| 79 | compatible: |
| 80 | contains: |
| 81 | enum: |
| 82 | - rockchip,rk3568-dwc-ahci |
| 83 | then: |
| 84 | properties: |
| 85 | clocks: |
| 86 | maxItems: 3 |
| 87 | clock-names: |
| 88 | items: |
| 89 | - const: sata |
| 90 | - const: pmalive |
| 91 | - const: rxoob |
| 92 | |
| 93 | unevaluatedProperties: false |
| 94 | |
| 95 | examples: |
| 96 | - | |
| 97 | #include <dt-bindings/clock/rockchip,rk3588-cru.h> |
| 98 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 99 | #include <dt-bindings/ata/ahci.h> |
| 100 | #include <dt-bindings/phy/phy.h> |
| 101 | |
| 102 | sata@fe210000 { |
| 103 | compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; |
| 104 | reg = <0xfe210000 0x1000>; |
| 105 | clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, |
| 106 | <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, |
| 107 | <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; |
| 108 | clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; |
| 109 | interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; |
| 110 | ports-implemented = <0x1>; |
| 111 | #address-cells = <1>; |
| 112 | #size-cells = <0>; |
| 113 | |
| 114 | sata-port@0 { |
| 115 | reg = <0>; |
| 116 | hba-port-cap = <HBA_PORT_FBSCP>; |
| 117 | phys = <&combphy0_ps PHY_TYPE_SATA>; |
| 118 | phy-names = "sata-phy"; |
| 119 | snps,rx-ts-max = <32>; |
| 120 | snps,tx-ts-max = <32>; |
| 121 | }; |
| 122 | }; |
| 123 | |
| 124 | ... |