| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Hisilicon HiP06 Low Pin Count device |
| 8 | |
| 9 | maintainers: |
| 10 | - Wei Xu <xuwei5@hisilicon.com> |
| 11 | |
| 12 | description: | |
| 13 | Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which |
| 14 | provides I/O access to some legacy ISA devices. |
| 15 | HiP06 is based on arm64 architecture where there is no I/O space. So, the |
| 16 | I/O ports here are not CPU addresses, and there is no 'ranges' property in |
| 17 | LPC device node. |
| 18 | |
| 19 | properties: |
| 20 | $nodename: |
| 21 | pattern: '^isa@[0-9a-f]+$' |
| 22 | description: | |
| 23 | The node name before '@' must be "isa" to represent the binding stick |
| 24 | to the ISA/EISA binding specification. |
| 25 | |
| 26 | compatible: |
| 27 | enum: |
| 28 | - hisilicon,hip06-lpc |
| 29 | - hisilicon,hip07-lpc |
| 30 | |
| 31 | reg: |
| 32 | maxItems: 1 |
| 33 | |
| 34 | '#address-cells': |
| 35 | const: 2 |
| 36 | |
| 37 | '#size-cells': |
| 38 | const: 1 |
| 39 | |
| 40 | required: |
| 41 | - compatible |
| 42 | - reg |
| 43 | |
| 44 | additionalProperties: |
| 45 | type: object |
| 46 | |
| 47 | examples: |
| 48 | - | |
| 49 | isa@a01b0000 { |
| 50 | compatible = "hisilicon,hip06-lpc"; |
| 51 | #address-cells = <2>; |
| 52 | #size-cells = <1>; |
| 53 | reg = <0xa01b0000 0x1000>; |
| 54 | |
| 55 | ipmi0: bt@e4 { |
| 56 | compatible = "ipmi-bt"; |
| 57 | device_type = "ipmi"; |
| 58 | reg = <0x01 0xe4 0x04>; |
| 59 | }; |
| 60 | }; |
| 61 | ... |