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Lokesh Vutlaa2285322019-06-13 10:29:42 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * J721E: SoC specific initialization
4 *
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
7 */
8
9#include <common.h>
10#include <spl.h>
11#include <asm/io.h>
12#include <asm/armv7_mpu.h>
Lokesh Vutla6edde292019-06-13 10:29:43 +053013#include <asm/arch/hardware.h>
Lokesh Vutlaa2285322019-06-13 10:29:42 +053014#include "common.h"
15
16#ifdef CONFIG_SPL_BUILD
Andreas Dannenberg660aa462019-06-13 10:29:44 +053017static void mmr_unlock(u32 base, u32 partition)
18{
19 /* Translate the base address */
20 phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
21
22 /* Unlock the requested partition if locked using two-step sequence */
23 writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
24 writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
25}
26
27static void ctrl_mmr_unlock(void)
28{
29 /* Unlock all WKUP_CTRL_MMR0 module registers */
30 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
31 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
32 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
33 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
34 mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
35 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
36 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
37
38 /* Unlock all MCU_CTRL_MMR0 module registers */
39 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
40 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
41 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
42 mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
43 mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
44
45 /* Unlock all CTRL_MMR0 module registers */
46 mmr_unlock(CTRL_MMR0_BASE, 0);
47 mmr_unlock(CTRL_MMR0_BASE, 1);
48 mmr_unlock(CTRL_MMR0_BASE, 2);
49 mmr_unlock(CTRL_MMR0_BASE, 3);
50 mmr_unlock(CTRL_MMR0_BASE, 4);
51 mmr_unlock(CTRL_MMR0_BASE, 5);
52 mmr_unlock(CTRL_MMR0_BASE, 6);
53 mmr_unlock(CTRL_MMR0_BASE, 7);
54}
55
Lokesh Vutlaa2285322019-06-13 10:29:42 +053056void board_init_f(ulong dummy)
57{
58 /*
59 * ToDo:
60 * - Store boot rom index.
Lokesh Vutlaa2285322019-06-13 10:29:42 +053061 */
62
Andreas Dannenberg660aa462019-06-13 10:29:44 +053063 /* Make all control module registers accessible */
64 ctrl_mmr_unlock();
65
Lokesh Vutlaa2285322019-06-13 10:29:42 +053066#ifdef CONFIG_CPU_V7R
67 setup_k3_mpu_regions();
68#endif
69
70 /* Init DM early */
71 spl_early_init();
72
73 /* Prepare console output */
74 preloader_console_init();
75}
Lokesh Vutla6edde292019-06-13 10:29:43 +053076
77u32 spl_boot_mode(const u32 boot_device)
78{
79 switch (boot_device) {
80 case BOOT_DEVICE_MMC1:
81 return MMCSD_MODE_EMMCBOOT;
82 case BOOT_DEVICE_MMC2:
83 return MMCSD_MODE_FS;
84 default:
85 return MMCSD_MODE_RAW;
86 }
87}
88
89static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
90{
91
92 u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
93 WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
94
95 bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
96 BOOT_MODE_B_SHIFT;
97
98 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
99 bootmode = BOOT_DEVICE_SPI;
100
101 if (bootmode == BOOT_DEVICE_MMC2) {
102 u32 port = (main_devstat &
103 MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
104 MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
105 if (port == 0x0)
106 bootmode = BOOT_DEVICE_MMC1;
107 }
108
109 return bootmode;
110}
111
112u32 spl_boot_device(void)
113{
114 u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
115 u32 main_devstat;
116
117 if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
118 printf("ERROR: MCU only boot is not yet supported\n");
119 return BOOT_DEVICE_RAM;
120 }
121
122 /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
123 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
124
125 /* ToDo: Add support for backup boot media */
126 return __get_primary_bootmedia(main_devstat, wkup_devstat);
127}
Lokesh Vutlaa2285322019-06-13 10:29:42 +0530128#endif