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git01.mediatek.com / filogic / uboot / 66023c7e5af66cacf27595c8b5c20e63a38c41dc / . / arch / powerpc / cpu / mpc8xxx / ddr / Makefile
blob: 8cbc06c95a0665035304f2e47d7904a88b54dd98 [file] [log] [blame]
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]1#
York Sunbd495cf2011-09-16 13:21:35 -0700[diff] [blame]2# Copyright 2008-2011 Freescale Semiconductor, Inc.
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]3#
4# This program is free software; you can redistribute it and/or
5# modify it under the terms of the GNU General Public License
6# Version 2 as published by the Free Software Foundation.
7#
8
Masahiro Yamada4fbb29d2013-10-17 17:35:04 +0900[diff] [blame]9obj-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]10 lc_common_dimm_params.o
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]11
Masahiro Yamada4fbb29d2013-10-17 17:35:04 +0900[diff] [blame]12obj-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]13 lc_common_dimm_params.o
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]14
Masahiro Yamada4fbb29d2013-10-17 17:35:04 +0900[diff] [blame]15obj-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
Dave Liu4be87b22009-03-14 12:48:30 +0800[diff] [blame]16 lc_common_dimm_params.o
York Sune73cc042011-06-07 09:42:16 +0800[diff] [blame]17ifdef CONFIG_DDR_SPD
18SPD := y
19endif
20ifdef CONFIG_SPD_EEPROM
21SPD := y
22endif
23ifdef SPD
Masahiro Yamada4fbb29d2013-10-17 17:35:04 +0900[diff] [blame]24obj-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o
25obj-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o
26obj-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o
York Sune73cc042011-06-07 09:42:16 +0800[diff] [blame]27endif
28
Masahiro Yamada4fbb29d2013-10-17 17:35:04 +0900[diff] [blame]29obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o