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wdenkbb1b8262003-03-27 12:09:35 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkbb1b8262003-03-27 12:09:35 +00006 */
7
8#include <common.h>
9#include <asm/inca-ip.h>
10
11
wdenkbb1b8262003-03-27 12:09:35 +000012/*******************************************************************************
13*
wdenk57b2d802003-06-27 21:31:46 +000014* get_cpuclk - returns the frequency of the CPU.
wdenkbb1b8262003-03-27 12:09:35 +000015*
16* Gets the value directly from the INCA-IP hardware.
17*
wdenk57b2d802003-06-27 21:31:46 +000018* RETURNS:
wdenkbb1b8262003-03-27 12:09:35 +000019* 150.000.000 for 150 MHz
Wolfgang Denkaf0501a2008-10-19 02:35:50 +020020* 133.333.333 for 133 MHz (= 400MHz/3)
21* 100.000.000 for 100 MHz (= 400MHz/4)
wdenkbb1b8262003-03-27 12:09:35 +000022* NOTE:
23* This functions should be used by the hardware driver to get the correct
24* frequency of the CPU. Don't use the macros, which are set to init the CPU
25* frequency in the ROM code.
26*/
wdenkaeae3a12003-12-27 19:29:48 +000027uint incaip_get_cpuclk (void)
wdenkbb1b8262003-03-27 12:09:35 +000028{
wdenkaeae3a12003-12-27 19:29:48 +000029 /*-------------------------------------------------------------------------*/
30 /* CPU Clock Input Multiplexer (MUX I) */
31 /* Multiplexer MUX I selects the maximum input clock to the CPU. */
32 /*-------------------------------------------------------------------------*/
33 if (*((volatile ulong *) INCA_IP_CGU_CGU_MUXCR) &
34 INCA_IP_CGU_CGU_MUXCR_MUXI) {
35 /* MUX I set to 150 MHz clock */
36 return 150000000;
37 } else {
38 /* MUX I set to 100/133 MHz clock */
39 if (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0x40) {
40 /* Division value is 1/3, maximum CPU operating */
41 /* frequency is 133.3 MHz */
wdenk398eeff2004-01-21 20:46:28 +000042 return 133333333;
wdenkaeae3a12003-12-27 19:29:48 +000043 } else {
44 /* Division value is 1/4, maximum CPU operating */
45 /* frequency is 100 MHz */
46 return 100000000;
47 }
48 }
wdenkbb1b8262003-03-27 12:09:35 +000049}
50
51/*******************************************************************************
52*
wdenk57b2d802003-06-27 21:31:46 +000053* get_fpiclk - returns the frequency of the FPI bus.
wdenkbb1b8262003-03-27 12:09:35 +000054*
55* Gets the value directly from the INCA-IP hardware.
56*
57* RETURNS: Frquency in Hz
58*
59* NOTE:
60* This functions should be used by the hardware driver to get the correct
61* frequency of the CPU. Don't use the macros, which are set to init the CPU
62* frequency in the ROM code.
wdenk57b2d802003-06-27 21:31:46 +000063* The calculation for the
wdenkbb1b8262003-03-27 12:09:35 +000064*/
wdenkaeae3a12003-12-27 19:29:48 +000065uint incaip_get_fpiclk (void)
wdenkbb1b8262003-03-27 12:09:35 +000066{
wdenkaeae3a12003-12-27 19:29:48 +000067 uint clkCPU;
wdenk57b2d802003-06-27 21:31:46 +000068
wdenkaeae3a12003-12-27 19:29:48 +000069 clkCPU = incaip_get_cpuclk ();
wdenk57b2d802003-06-27 21:31:46 +000070
wdenkaeae3a12003-12-27 19:29:48 +000071 switch (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0xC) {
72 case 0x4:
73 return clkCPU >> 1; /* devided by 2 */
74 break;
75 case 0x8:
76 return clkCPU >> 2; /* devided by 4 */
77 break;
78 default:
79 return clkCPU;
80 break;
81 }
wdenkbb1b8262003-03-27 12:09:35 +000082}
wdenk67f13362003-12-27 19:24:54 +000083
wdenkaeae3a12003-12-27 19:29:48 +000084int incaip_set_cpuclk (void)
wdenk67f13362003-12-27 19:24:54 +000085{
wdenkaeae3a12003-12-27 19:29:48 +000086 extern void ebu_init(long);
87 extern void cgu_init(long);
wdenk433feff2004-01-29 09:22:58 +000088 extern void sdram_init(long);
Wolfgang Denkf6a692b2005-12-04 00:40:34 +010089 char tmp[64];
wdenk67f13362003-12-27 19:24:54 +000090 ulong cpuclk;
91
Wolfgang Denk76af2782010-07-24 21:55:43 +020092 if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) {
wdenkaeae3a12003-12-27 19:29:48 +000093 cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
wdenkaeae3a12003-12-27 19:29:48 +000094 cgu_init (cpuclk);
wdenk433feff2004-01-29 09:22:58 +000095 ebu_init (cpuclk);
96 sdram_init (cpuclk);
wdenk67f13362003-12-27 19:24:54 +000097 }
98
99 return 0;
100}