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wdenke887afc2002-08-27 09:44:07 +00001/*
2 * (C) Copyright 2000
3 * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenke887afc2002-08-27 09:44:07 +00006 */
7
8#include <common.h>
9#include <command.h>
Heiko Schocher65d94db2017-06-07 17:33:09 +020010#if defined (CONFIG_4xx)
Niklaus Gigerd4c61542009-10-04 20:04:21 +020011extern void ppc4xx_reginfo(void);
wdenk359733b2003-03-31 17:27:09 +000012#elif defined (CONFIG_5xx)
13#include <mpc5xx.h>
wdenk64519362004-07-11 17:40:54 +000014#elif defined (CONFIG_MPC5200)
15#include <mpc5xxx.h>
Becky Bruceb0b30942008-01-23 16:31:06 -060016#elif defined (CONFIG_MPC86xx)
17extern void mpc86xx_reginfo(void);
Becky Bruceee888da2010-06-17 11:37:25 -050018#elif defined(CONFIG_MPC85xx)
19extern void mpc85xx_reginfo(void);
wdenke887afc2002-08-27 09:44:07 +000020#endif
Jon Loeliger3de8b242007-06-11 19:01:54 -050021
Kim Phillipsdc00a682012-10-29 13:34:31 +000022static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
23 char * const argv[])
wdenke887afc2002-08-27 09:44:07 +000024{
Heiko Schocher65d94db2017-06-07 17:33:09 +020025#if defined (CONFIG_4xx)
Niklaus Gigerd4c61542009-10-04 20:04:21 +020026 ppc4xx_reginfo();
wdenk359733b2003-03-31 17:27:09 +000027#elif defined(CONFIG_5xx)
wdenke887afc2002-08-27 09:44:07 +000028
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020029 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
wdenk359733b2003-03-31 17:27:09 +000030 volatile memctl5xx_t *memctl = &immap->im_memctl;
31 volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
32 volatile sit5xx_t *timers = &immap->im_sit;
33 volatile car5xx_t *car = &immap->im_clkrst;
34 volatile uimb5xx_t *uimb = &immap->im_uimb;
35
wdenk42c05472004-03-23 22:14:11 +000036 puts ("\nSystem Configuration registers\n");
wdenk359733b2003-03-31 17:27:09 +000037 printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
38 printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
39 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
40 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
41 printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
42
wdenk42c05472004-03-23 22:14:11 +000043 puts ("\nMemory Controller Registers\n");
wdenk359733b2003-03-31 17:27:09 +000044 printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
45 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
46 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
47 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
48 printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
49 printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
50
wdenk42c05472004-03-23 22:14:11 +000051 puts ("\nSystem Integration Timers\n");
wdenk359733b2003-03-31 17:27:09 +000052 printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
53 printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
54
wdenk42c05472004-03-23 22:14:11 +000055 puts ("\nClocks and Reset\n");
wdenk359733b2003-03-31 17:27:09 +000056 printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
57
wdenk42c05472004-03-23 22:14:11 +000058 puts ("\nU-Bus to IMB3 Bus Interface\n");
wdenk359733b2003-03-31 17:27:09 +000059 printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
wdenk42c05472004-03-23 22:14:11 +000060 puts ("\n\n");
wdenk64519362004-07-11 17:40:54 +000061
62#elif defined(CONFIG_MPC5200)
63 puts ("\nMPC5200 registers\n");
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064 printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
wdenk64519362004-07-11 17:40:54 +000065 puts ("Memory map registers\n");
Wolfgang Denk12cec0a2008-07-11 01:16:00 +020066 printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk64519362004-07-11 17:40:54 +000067 *(volatile ulong*)MPC5XXX_CS0_START,
68 *(volatile ulong*)MPC5XXX_CS0_STOP,
69 *(volatile ulong*)MPC5XXX_CS0_CFG,
70 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
Wolfgang Denk12cec0a2008-07-11 01:16:00 +020071 printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk64519362004-07-11 17:40:54 +000072 *(volatile ulong*)MPC5XXX_CS1_START,
73 *(volatile ulong*)MPC5XXX_CS1_STOP,
74 *(volatile ulong*)MPC5XXX_CS1_CFG,
75 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
Wolfgang Denk12cec0a2008-07-11 01:16:00 +020076 printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk64519362004-07-11 17:40:54 +000077 *(volatile ulong*)MPC5XXX_CS2_START,
78 *(volatile ulong*)MPC5XXX_CS2_STOP,
79 *(volatile ulong*)MPC5XXX_CS2_CFG,
80 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
Wolfgang Denk12cec0a2008-07-11 01:16:00 +020081 printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk64519362004-07-11 17:40:54 +000082 *(volatile ulong*)MPC5XXX_CS3_START,
83 *(volatile ulong*)MPC5XXX_CS3_STOP,
84 *(volatile ulong*)MPC5XXX_CS3_CFG,
85 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
Wolfgang Denk12cec0a2008-07-11 01:16:00 +020086 printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk64519362004-07-11 17:40:54 +000087 *(volatile ulong*)MPC5XXX_CS4_START,
88 *(volatile ulong*)MPC5XXX_CS4_STOP,
89 *(volatile ulong*)MPC5XXX_CS4_CFG,
90 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
Wolfgang Denk12cec0a2008-07-11 01:16:00 +020091 printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk64519362004-07-11 17:40:54 +000092 *(volatile ulong*)MPC5XXX_CS5_START,
93 *(volatile ulong*)MPC5XXX_CS5_STOP,
94 *(volatile ulong*)MPC5XXX_CS5_CFG,
95 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
Wolfgang Denk12cec0a2008-07-11 01:16:00 +020096 printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk64519362004-07-11 17:40:54 +000097 *(volatile ulong*)MPC5XXX_CS6_START,
98 *(volatile ulong*)MPC5XXX_CS6_STOP,
99 *(volatile ulong*)MPC5XXX_CS6_CFG,
100 (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
Wolfgang Denk12cec0a2008-07-11 01:16:00 +0200101 printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk64519362004-07-11 17:40:54 +0000102 *(volatile ulong*)MPC5XXX_CS7_START,
103 *(volatile ulong*)MPC5XXX_CS7_STOP,
104 *(volatile ulong*)MPC5XXX_CS7_CFG,
105 (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
Wolfgang Denk12cec0a2008-07-11 01:16:00 +0200106 printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk64519362004-07-11 17:40:54 +0000107 *(volatile ulong*)MPC5XXX_BOOTCS_START,
108 *(volatile ulong*)MPC5XXX_BOOTCS_STOP,
109 *(volatile ulong*)MPC5XXX_BOOTCS_CFG,
110 (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
Wolfgang Denk12cec0a2008-07-11 01:16:00 +0200111 printf ("\tSDRAMCS0: %08lX\n",
wdenk64519362004-07-11 17:40:54 +0000112 *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
Wolfgang Denk12cec0a2008-07-11 01:16:00 +0200113 printf ("\tSDRAMCS1: %08lX\n",
wdenk64519362004-07-11 17:40:54 +0000114 *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
Becky Bruceb0b30942008-01-23 16:31:06 -0600115#elif defined(CONFIG_MPC86xx)
116 mpc86xx_reginfo();
Mike Frysinger030f3452008-02-04 19:26:56 -0500117
Becky Bruceee888da2010-06-17 11:37:25 -0500118#elif defined(CONFIG_MPC85xx)
119 mpc85xx_reginfo();
Sonic Zhanga99f03e2012-08-16 11:56:14 +0800120#endif
Becky Bruceb0b30942008-01-23 16:31:06 -0600121
wdenke887afc2002-08-27 09:44:07 +0000122 return 0;
123}
124
wdenk57b2d802003-06-27 21:31:46 +0000125 /**************************************************/
126
Mike Frysinger030f3452008-02-04 19:26:56 -0500127#if defined(CONFIG_CMD_REGINFO)
wdenkf287a242003-07-01 21:06:45 +0000128U_BOOT_CMD(
Wolfgang Denka1be4762008-05-20 16:00:29 +0200129 reginfo, 2, 1, do_reginfo,
Peter Tyserdfb72b82009-01-27 18:03:12 -0600130 "print register information",
Wolfgang Denkc54781c2009-05-24 17:06:54 +0200131 ""
wdenk57b2d802003-06-27 21:31:46 +0000132);
133#endif