| Ye Li | b2cfc42 | 2022-07-26 16:41:07 +0800 | [diff] [blame] | 1 | menu "i.MX9 DDR controllers" |
| 2 | depends on ARCH_IMX9 |
| 3 | |
| 4 | config IMX9_DRAM |
| 5 | bool "imx9 dram" |
| 6 | select IMX_SNPS_DDR_PHY |
| 7 | |
| 8 | config IMX9_LPDDR4X |
| 9 | bool "imx9 lpddr4 and lpddr4x" |
| 10 | select IMX9_DRAM |
| 11 | help |
| 12 | Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC. |
| 13 | |
| Ye Li | f188a4f | 2022-07-26 16:41:08 +0800 | [diff] [blame] | 14 | config IMX9_DRAM_PM_COUNTER |
| 15 | bool "imx9 DDRC performance monitor counter" |
| 16 | default y |
| 17 | help |
| 18 | Enable DDR controller performance monitor counter for reference events. |
| 19 | |
| Peng Fan | e2c7643 | 2024-10-23 12:03:17 +0800 | [diff] [blame] | 20 | config IMX9_DRAM_INLINE_ECC |
| 21 | bool "Enable DDR INLINE ECC feature" |
| 22 | help |
| 23 | Select to enable DDR INLINE ECC feature |
| 24 | |
| Ye Li | b2cfc42 | 2022-07-26 16:41:07 +0800 | [diff] [blame] | 25 | config SAVED_DRAM_TIMING_BASE |
| 26 | hex "Define the base address for saved dram timing" |
| 27 | help |
| 28 | after DRAM is trained, need to save the dram related timming |
| 29 | info into memory for low power use. |
| Jacky Bai | 8d1ce4b | 2023-04-28 12:08:41 +0800 | [diff] [blame] | 30 | default 0x2051C000 |
| Ye Li | b2cfc42 | 2022-07-26 16:41:07 +0800 | [diff] [blame] | 31 | |
| 32 | endmenu |