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git01.mediatek.com / filogic / uboot / 65aa1246afa5d1de145c92d6c1121396fbece3f0 / . / configs / sama5d2_xplained_qspiflash_defconfig
blob: 9bb838ca893c861dd2c5a5dd64e9eff4aa01ded5 [file] [log] [blame]
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Adam Fordd36b1022019-08-14 08:29:25 -0500[diff] [blame]3CONFIG_ARCH_CPU_INIT=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]4CONFIG_ARCH_AT91=y
5CONFIG_SYS_TEXT_BASE=0x26f00000
6CONFIG_TARGET_SAMA5D2_XPLAINED=y
Simon Glass035939e2021-07-10 21:14:30 -0600[diff] [blame]7CONFIG_SPL_GPIO=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]8CONFIG_SPL_LIBCOMMON_SUPPORT=y
9CONFIG_SPL_LIBGENERIC_SUPPORT=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]10CONFIG_NR_DRAM_BANKS=1
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]11CONFIG_ENV_SECT_SIZE=0x1000
12CONFIG_DM_GPIO=y
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]13CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]14CONFIG_SPL_TEXT_BASE=0x200000
Simon Glassb58bfe02021-08-08 12:20:09 -0600[diff] [blame]15CONFIG_SPL_MMC=y
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]16CONFIG_SPL_SERIAL=y
Simon Glass284cb9c2021-07-10 21:14:31 -0600[diff] [blame]17CONFIG_SPL_DRIVERS_MISC=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]18CONFIG_SPL=y
19CONFIG_DEBUG_UART_BOARD_INIT=y
20CONFIG_DEBUG_UART_BASE=0xf8020000
21CONFIG_DEBUG_UART_CLOCK=83000000
22CONFIG_SPL_FS_FAT=y
23CONFIG_SPL_LIBDISK_SUPPORT=y
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]24CONFIG_SYS_LOAD_ADDR=0x22000000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]25CONFIG_DEBUG_UART=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]26CONFIG_ENV_VARS_UBOOT_CONFIG=y
Tom Rini4ddbade2022-05-25 12:16:03 -0400[diff] [blame]27CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
28CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]29CONFIG_FIT=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]30CONFIG_QSPI_BOOT=y
Tom Rini9ec25872022-03-24 17:18:03 -0400[diff] [blame]31CONFIG_SD_BOOT=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]32CONFIG_BOOTDELAY=3
33CONFIG_USE_BOOTARGS=y
34CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait"
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]35CONFIG_USE_BOOTCOMMAND=y
36CONFIG_BOOTCOMMAND="sf probe 1:0; sf read 0x22000000 0x180000 0x80000; sf read 0x23000000 0x200000 0x600000; bootz 0x23000000 - 0x22000000"
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]37# CONFIG_DISPLAY_BOARDINFO is not set
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]38CONFIG_MISC_INIT_R=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]39CONFIG_SPL_MAX_SIZE=0x10000
Tom Rini65aa1242022-05-27 10:19:45 -0400[diff] [blame^]40CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
41CONFIG_SPL_BSS_START_ADDR=0x20000000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]42CONFIG_SPL_BSS_MAX_SIZE=0x80000
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]43# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
44CONFIG_SPL_STACK=0x218000
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]45CONFIG_HUSH_PARSER=y
Tom Riniae17fa32022-05-11 18:01:06 -0400[diff] [blame]46CONFIG_SYS_CBSIZE=256
Tom Rinicbfa1392022-05-11 17:38:09 -0400[diff] [blame]47CONFIG_SYS_PBSIZE=276
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]48CONFIG_CMD_BOOTZ=y
Mihai Sainbb41f992021-09-02 15:21:08 +0300[diff] [blame]49CONFIG_CMD_DM=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]50# CONFIG_CMD_FLASH is not set
Tom Rinib3e3fe42021-12-27 13:53:48 +0000[diff] [blame]51CONFIG_CMD_GPIO=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]52CONFIG_CMD_I2C=y
53# CONFIG_CMD_LOADS is not set
54CONFIG_CMD_MMC=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]55CONFIG_CMD_USB=y
56CONFIG_CMD_DHCP=y
Tom Rini1c47c4a2022-02-25 11:19:50 -0500[diff] [blame]57CONFIG_BOOTP_BOOTFILESIZE=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]58CONFIG_CMD_PING=y
Eugen Hristev858f8d52021-05-26 16:05:57 +0300[diff] [blame]59CONFIG_CMD_HASH=y
60CONFIG_HASH_VERIFY=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]61CONFIG_CMD_EXT4=y
62CONFIG_CMD_FAT=y
63CONFIG_OF_CONTROL=y
64CONFIG_SPL_OF_CONTROL=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]65CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
66CONFIG_ENV_IS_IN_SPI_FLASH=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]67CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]68CONFIG_DM=y
69CONFIG_SPL_DM=y
70CONFIG_SPL_DM_SEQ_ALIAS=y
71CONFIG_CLK=y
72CONFIG_SPL_CLK=y
73CONFIG_CLK_AT91=y
74CONFIG_AT91_UTMI=y
75CONFIG_AT91_H32MX=y
76CONFIG_AT91_GENERIC_CLK=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]77CONFIG_ATMEL_PIO4=y
78CONFIG_DM_I2C=y
79CONFIG_SYS_I2C_AT91=y
80CONFIG_I2C_EEPROM=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]81CONFIG_MMC_SDHCI=y
82CONFIG_MMC_SDHCI_ATMEL=y
Miquel Raynal803baa22019-10-03 19:50:08 +0200[diff] [blame]83CONFIG_MTD=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]84CONFIG_DM_SPI_FLASH=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]85CONFIG_SF_DEFAULT_SPEED=30000000
86CONFIG_SPI_FLASH_ATMEL=y
87CONFIG_SPI_FLASH_MACRONIX=y
88CONFIG_SPI_FLASH_SPANSION=y
89CONFIG_SPI_FLASH_STMICRO=y
90CONFIG_SPI_FLASH_SST=y
91CONFIG_DM_ETH=y
92CONFIG_MACB=y
93CONFIG_PINCTRL=y
94CONFIG_SPL_PINCTRL=y
95CONFIG_PINCTRL_AT91PIO4=y
96CONFIG_DM_SERIAL=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]97CONFIG_DEBUG_UART_ANNOUNCE=y
98CONFIG_ATMEL_USART=y
99CONFIG_SPI=y
100CONFIG_DM_SPI=y
101CONFIG_ATMEL_QSPI=y
Sergiu Moga84567d42022-04-01 12:27:25 +0300[diff] [blame]102CONFIG_SYSRESET=y
103CONFIG_SPL_SYSRESET=y
Sergiu Moga84567d42022-04-01 12:27:25 +0300[diff] [blame]104CONFIG_SYSRESET_AT91=y
Tom Rini59d1a712022-05-05 14:47:31 -0400[diff] [blame]105CONFIG_TIMER=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]106CONFIG_SPL_TIMER=y
Clément Légerf26721b2022-03-31 10:55:10 +0200[diff] [blame]107CONFIG_ATMEL_TCB_TIMER=y
Eugen Hristev118141e2022-04-04 11:35:50 +0300[diff] [blame]108CONFIG_SPL_ATMEL_TCB_TIMER=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]109CONFIG_USB=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]110CONFIG_USB_EHCI_HCD=y
111CONFIG_USB_STORAGE=y
112CONFIG_USB_GADGET=y
113CONFIG_USB_GADGET_ATMEL_USBA=y
114CONFIG_DM_VIDEO=y
Anatolij Gustschindba36702020-02-04 22:43:06 +0100[diff] [blame]115# CONFIG_VIDEO_BPP8 is not set
116# CONFIG_VIDEO_BPP32 is not set
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]117CONFIG_ATMEL_HLCD=y
118CONFIG_W1=y
119CONFIG_W1_GPIO=y
120CONFIG_W1_EEPROM=y
121CONFIG_W1_EEPROM_DS24XXX=y
Tudor Ambarusf48ae102019-06-18 08:52:03 +0000[diff] [blame]122CONFIG_OF_LIBFDT_OVERLAY=y