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git01.mediatek.com / filogic / uboot / 65aa1246afa5d1de145c92d6c1121396fbece3f0 / . / configs / khadas-edge-v-rk3399_defconfig
blob: 731fbfcab2648efd1ec3145a72792fe07b28679c [file] [log] [blame]
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Peng Fanc8a61c02022-04-13 17:47:20 +0800[diff] [blame]3CONFIG_COUNTER_FREQUENCY=24000000
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
5CONFIG_SYS_TEXT_BASE=0x00200000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]6CONFIG_NR_DRAM_BANKS=1
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]7CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]8CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-v"
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]9CONFIG_ROCKCHIP_RK3399=y
Kever Yang1b662092020-02-19 17:51:07 +0800[diff] [blame]10CONFIG_TARGET_EVB_RK3399=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]11CONFIG_DEBUG_UART_BASE=0xFF1A0000
12CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]13CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]14CONFIG_DEBUG_UART=y
Tom Rini4ddbade2022-05-25 12:16:03 -0400[diff] [blame]15CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
16CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
Jared Baldridge0db396b2020-02-06 19:53:14 -0800[diff] [blame]17CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb"
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]18CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]19CONFIG_SPL_MAX_SIZE=0x2e000
20CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini65aa1242022-05-27 10:19:45 -0400[diff] [blame^]21CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
22CONFIG_SPL_BSS_START_ADDR=0x400000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]23CONFIG_SPL_BSS_MAX_SIZE=0x2000
Kever Yang20673542019-08-20 11:47:02 +0800[diff] [blame]24# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]25# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
26CONFIG_SPL_STACK=0x400000
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]27CONFIG_SPL_STACK_R=y
28CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
29CONFIG_TPL=y
30CONFIG_SYS_PROMPT="kedge# "
Tom Rinicbfa1392022-05-11 17:38:09 -0400[diff] [blame]31CONFIG_SYS_PBSIZE=1048
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]32CONFIG_CMD_BOOTZ=y
33CONFIG_CMD_GPT=y
34CONFIG_CMD_MMC=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]35CONFIG_CMD_USB=y
36# CONFIG_CMD_SETEXPR is not set
37CONFIG_CMD_TIME=y
38CONFIG_SPL_OF_CONTROL=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]39CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
40CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]41CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]42CONFIG_NET_RANDOM_ETHADDR=y
43CONFIG_ROCKCHIP_GPIO=y
44CONFIG_SYS_I2C_ROCKCHIP=y
45CONFIG_MMC_DW=y
46CONFIG_MMC_DW_ROCKCHIP=y
47CONFIG_MMC_SDHCI=y
48CONFIG_MMC_SDHCI_ROCKCHIP=y
49CONFIG_PHY_REALTEK=y
50CONFIG_DM_ETH=y
51CONFIG_ETH_DESIGNWARE=y
52CONFIG_GMAC_ROCKCHIP=y
53CONFIG_PMIC_RK8XX=y
54CONFIG_REGULATOR_PWM=y
55CONFIG_REGULATOR_RK8XX=y
56CONFIG_PWM_ROCKCHIP=y
57CONFIG_RAM_RK3399_LPDDR4=y
58CONFIG_BAUDRATE=1500000
59CONFIG_DEBUG_UART_SHIFT=2
60CONFIG_SYSRESET=y
61CONFIG_USB=y
62CONFIG_USB_XHCI_HCD=y
63CONFIG_USB_XHCI_DWC3=y
64CONFIG_USB_EHCI_HCD=y
65CONFIG_USB_EHCI_GENERIC=y
Artem Lapkin3227ecb2021-06-07 11:45:05 +0800[diff] [blame]66CONFIG_USB_OHCI_HCD=y
67CONFIG_USB_OHCI_GENERIC=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]68CONFIG_USB_HOST_ETHER=y
69CONFIG_USB_ETHER_ASIX=y
70CONFIG_USB_ETHER_ASIX88179=y
71CONFIG_USB_ETHER_MCS7830=y
72CONFIG_USB_ETHER_RTL8152=y
73CONFIG_USB_ETHER_SMSC95XX=y
74CONFIG_SPL_TINY_MEMSET=y
75CONFIG_ERRNO_STR=y