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git01.mediatek.com / filogic / uboot / 659c9cdb308d10d18b1aa3343ca453713234e852 / . / include / fsl_pmic.h
blob: 64c1e2ef65e15bab8f9f5aaf0a6cdb4b1fee6c5a [file] [log] [blame]
Stefano Babic6a0034d2010-04-04 23:08:03 +0200[diff] [blame]1/*
2 * (C) Copyright 2010
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __FSL_PMIC_H__
27#define __FSL_PMIC_H__
28
29/*
30 * The registers of different PMIC has the same meaning
31 * but the bit positions of the fields can differ or
32 * some fields has a meaning only on some devices.
33 * You have to check with the internal SPI bitmap
34 * (see Freescale Documentation) to set the registers
35 * for the device you are using
36 */
37enum {
38 REG_INT_STATUS0 = 0,
39 REG_INT_MASK0,
40 REG_INT_SENSE0,
41 REG_INT_STATUS1,
42 REG_INT_MASK1,
43 REG_INT_SENSE1,
44 REG_PU_MODE_S,
45 REG_IDENTIFICATION,
46 REG_UNUSED0,
47 REG_ACC0,
48 REG_ACC1, /*10 */
49 REG_UNUSED1,
50 REG_UNUSED2,
51 REG_POWER_CTL0,
52 REG_POWER_CTL1,
53 REG_POWER_CTL2,
54 REG_REGEN_ASSIGN,
55 REG_UNUSED3,
56 REG_MEM_A,
57 REG_MEM_B,
58 REG_RTC_TIME, /*20 */
59 REG_RTC_ALARM,
60 REG_RTC_DAY,
61 REG_RTC_DAY_ALARM,
62 REG_SW_0,
63 REG_SW_1,
64 REG_SW_2,
65 REG_SW_3,
66 REG_SW_4,
67 REG_SW_5,
68 REG_SETTING_0, /*30 */
69 REG_SETTING_1,
70 REG_MODE_0,
71 REG_MODE_1,
72 REG_POWER_MISC,
73 REG_UNUSED4,
74 REG_UNUSED5,
75 REG_UNUSED6,
76 REG_UNUSED7,
77 REG_UNUSED8,
78 REG_UNUSED9, /*40 */
79 REG_UNUSED10,
80 REG_UNUSED11,
81 REG_ADC0,
82 REG_ADC1,
83 REG_ADC2,
84 REG_ADC3,
85 REG_ADC4,
86 REG_CHARGE,
87 REG_USB0,
88 REG_USB1, /*50 */
89 REG_LED_CTL0,
90 REG_LED_CTL1,
91 REG_LED_CTL2,
92 REG_LED_CTL3,
93 REG_UNUSED12,
94 REG_UNUSED13,
95 REG_TRIM0,
96 REG_TRIM1,
97 REG_TEST0,
98 REG_TEST1, /*60 */
99 REG_TEST2,
100 REG_TEST3,
101 REG_TEST4,
Stefano Babic222be652011-10-05 12:38:27 +0200[diff] [blame]102 PMIC_NUM_OF_REGS,
Stefano Babic6a0034d2010-04-04 23:08:03 +0200[diff] [blame]103};
104
105/* REG_POWER_MISC */
106#define GPO1EN (1 << 6)
107#define GPO1STBY (1 << 7)
108#define GPO2EN (1 << 8)
109#define GPO2STBY (1 << 9)
110#define GPO3EN (1 << 10)
111#define GPO3STBY (1 << 11)
112#define GPO4EN (1 << 12)
113#define GPO4STBY (1 << 13)
114#define PWGT1SPIEN (1 << 15)
115#define PWGT2SPIEN (1 << 16)
116#define PWUP (1 << 21)
117
118/* Power Control 0 */
119#define COINCHEN (1 << 23)
120#define BATTDETEN (1 << 19)
121
122/* Interrupt status 1 */
123#define RTCRSTI (1 << 7)
124
Fabio Estevam082a1122012-05-07 10:25:59 +0000[diff] [blame]125/* MC34708 Definitions */
126#define SWx_VOLT_MASK_MC34708 0x3F
127#define SWx_1_250V_MC34708 0x30
128#define SWx_1_300V_MC34708 0x34
129#define TIMER_MASK_MC34708 0x300
130#define TIMER_4S_MC34708 0x100
131#define VUSBSEL_MC34708 (1 << 2)
132#define VUSBEN_MC34708 (1 << 3)
133#define SWBST_CTRL 31
Fabio Estevam0436b7a2012-05-07 10:26:00 +0000[diff] [blame]134#define SWBST_AUTO 0x8
Fabio Estevam082a1122012-05-07 10:25:59 +0000[diff] [blame]135
Stefano Babic6a0034d2010-04-04 23:08:03 +0200[diff] [blame]136#endif