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git01.mediatek.com / filogic / uboot / 65922b7925021f4823ec1204c3793324ed5a9621 / . / configs / nyan-big_defconfig
blob: 6435bad8ad62b76f8fe895bf403f930208751520 [file] [log] [blame]
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]1CONFIG_ARM=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]2CONFIG_SYS_L2CACHE_OFF=y
Trevor Woerner513f6402020-05-06 08:02:41 -0400[diff] [blame]3CONFIG_ARCH_TEGRA=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]4CONFIG_TEXT_BASE=0x81000100
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]5CONFIG_SYS_MALLOC_LEN=0x2500000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]6CONFIG_NR_DRAM_BANKS=2
Tom Rinia77d6f82023-05-01 11:50:26 -0400[diff] [blame]7CONFIG_SF_DEFAULT_SPEED=24000000
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]8CONFIG_ENV_SIZE=0x2000
9CONFIG_ENV_OFFSET=0xFFFFE000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]10CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]11CONFIG_SPL_TEXT_BASE=0x80108000
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]12CONFIG_SPL_STACK=0x800ffffc
Tom Rini66ea5c72019-05-26 14:45:25 -0400[diff] [blame]13CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]14CONFIG_DEBUG_UART_BASE=0x70006000
15CONFIG_DEBUG_UART_CLOCK=408000000
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]16CONFIG_TEGRA124=y
17CONFIG_TARGET_NYAN_BIG=y
Tom Rini4dbaf6f2022-06-08 08:24:33 -0400[diff] [blame]18CONFIG_TEGRA_GPU=y
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]19CONFIG_SYS_LOAD_ADDR=0x82408000
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]20CONFIG_DEBUG_UART=y
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]21CONFIG_FIT=y
22CONFIG_FIT_BEST_MATCH=y
23CONFIG_OF_SYSTEM_SETUP=y
Simon Glassa2037c52017-06-12 06:21:35 -0600[diff] [blame]24CONFIG_BOOTSTAGE=y
25CONFIG_SPL_BOOTSTAGE=y
26CONFIG_BOOTSTAGE_STASH=y
Simon Glass3110ece2016-10-17 20:13:02 -0600[diff] [blame]27CONFIG_SYS_STDIO_DEREGISTER=y
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]28CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]29CONFIG_SPL_FOOTPRINT_LIMIT=y
30CONFIG_SPL_MAX_FOOTPRINT=0xef8100
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]31# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
Tom Rini166e3222022-05-27 12:48:32 -0400[diff] [blame]32CONFIG_SYS_SPL_MALLOC=y
33CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
34CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
35CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
Tom Rinic4359852023-10-02 10:35:27 -0400[diff] [blame]36CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
Tom Riniba5c2b02022-05-11 16:21:06 -0400[diff] [blame]37CONFIG_SYS_MAXARGS=64
Tom Rinicbfa1392022-05-11 17:38:09 -0400[diff] [blame]38CONFIG_SYS_PBSIZE=2087
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]39# CONFIG_CMD_IMI is not set
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]40CONFIG_CMD_DFU=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]41CONFIG_CMD_GPIO=y
42CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]43CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]44CONFIG_CMD_SPI=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]45CONFIG_CMD_USB=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]46CONFIG_CMD_USB_MASS_STORAGE=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]47# CONFIG_CMD_SETEXPR is not set
Simon Glassb575bfc2017-04-26 22:27:55 -0600[diff] [blame]48CONFIG_CMD_BMP=y
Simon Glasseb7dc422017-05-31 17:57:19 -0600[diff] [blame]49CONFIG_CMD_CACHE=y
Simon Glass79d4ff52019-04-01 13:38:42 -0700[diff] [blame]50CONFIG_CMD_TIME=y
51CONFIG_CMD_SOUND=y
Tom Rinice34f5d2017-07-24 21:10:06 -0400[diff] [blame]52CONFIG_CMD_BOOTSTAGE=y
Simon Glassfad72182016-01-30 16:37:50 -0700[diff] [blame]53CONFIG_CMD_PMIC=y
54CONFIG_CMD_REGULATOR=y
Simon Glass1e823cf2015-08-22 18:31:44 -0600[diff] [blame]55CONFIG_CMD_TPM=y
56CONFIG_CMD_TPM_TEST=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]57CONFIG_CMD_EXT4_WRITE=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]58# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]59# CONFIG_SPL_EFI_PARTITION is not set
Simon Glass57d13382017-07-25 08:30:14 -0600[diff] [blame]60CONFIG_OF_LIVE=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]61CONFIG_ENV_OVERWRITE=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]62CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rinieb1f9092020-07-24 17:14:47 -0400[diff] [blame]63CONFIG_SYS_MMC_ENV_PART=2
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]64CONFIG_SPL_DM=y
Tom Rini265c7da2016-09-19 13:31:30 -0400[diff] [blame]65CONFIG_DFU_MMC=y
66CONFIG_DFU_RAM=y
67CONFIG_DFU_SF=y
Aswath Govindrajucc13c5d2021-06-01 16:51:47 +0530[diff] [blame]68CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
69CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
Tom Rini41b6dc92019-02-22 10:17:41 -0500[diff] [blame]70CONFIG_SYS_I2C_TEGRA=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]71CONFIG_CROS_EC_KEYB=y
Simon Glass3aa5d4a2015-06-05 14:39:34 -0600[diff] [blame]72CONFIG_CROS_EC=y
73CONFIG_CROS_EC_SPI=y
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]74CONFIG_SPI_FLASH_WINBOND=y
Simon Glassfad72182016-01-30 16:37:50 -0700[diff] [blame]75CONFIG_DM_PMIC=y
Simon Glass52222b12017-04-26 22:27:46 -0600[diff] [blame]76CONFIG_PMIC_AS3722=y
Simon Glassfad72182016-01-30 16:37:50 -0700[diff] [blame]77CONFIG_DM_REGULATOR=y
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]78CONFIG_REGULATOR_AS3722=y
Simon Glassfad72182016-01-30 16:37:50 -0700[diff] [blame]79CONFIG_DM_REGULATOR_FIXED=y
Simon Glass90836ff2016-01-30 16:38:00 -0700[diff] [blame]80CONFIG_PWM_TEGRA=y
Simon Glass4fcd26c2017-06-12 06:21:33 -0600[diff] [blame]81CONFIG_DEBUG_UART_SHIFT=2
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]82CONFIG_SYS_NS16550=y
Simon Glass79d4ff52019-04-01 13:38:42 -0700[diff] [blame]83CONFIG_SOUND=y
84CONFIG_I2S=y
85CONFIG_I2S_TEGRA=y
86CONFIG_SOUND_MAX98090=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]87CONFIG_TEGRA114_SPI=y
Christophe Ricard8759ff82015-10-06 22:54:41 +0200[diff] [blame]88CONFIG_TPM_TIS_INFINEON=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]89CONFIG_USB=y
Tom Rini7716cd62017-05-12 22:33:28 -0400[diff] [blame]90CONFIG_USB_EHCI_HCD=y
Peter Robinson43ecef42019-02-20 12:17:27 +0000[diff] [blame]91CONFIG_USB_EHCI_TEGRA=y
Tom Rini2c082ab2021-07-26 21:10:37 -0400[diff] [blame]92CONFIG_USB_HOST_ETHER=y
93CONFIG_USB_ETHER_ASIX=y
Sam Protsenkob084b0c2016-03-25 16:39:47 +0200[diff] [blame]94CONFIG_USB_GADGET=y
Sam Protsenkob4a0bf72016-04-13 14:20:25 +0300[diff] [blame]95CONFIG_CI_UDC=y
Sam Protsenko4d2439d2016-04-13 14:20:26 +0300[diff] [blame]96CONFIG_USB_GADGET_DOWNLOAD=y
Simon Glass52cb5042022-10-18 07:46:31 -0600[diff] [blame]97CONFIG_VIDEO=y
Anatolij Gustschindba36702020-02-04 22:43:06 +0100[diff] [blame]98# CONFIG_VIDEO_BPP8 is not set
99# CONFIG_VIDEO_BPP32 is not set
Bin Meng6dd8ddc2016-03-21 06:47:40 -0700[diff] [blame]100CONFIG_DISPLAY=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]101CONFIG_VIDEO_TEGRA124=y
Simon Glassfad72182016-01-30 16:37:50 -0700[diff] [blame]102CONFIG_VIDEO_BRIDGE=y
Simon Glasseb7dc422017-05-31 17:57:19 -0600[diff] [blame]103CONFIG_CMD_DHRYSTONE=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]104CONFIG_TPM=y
Simon Glassfad72182016-01-30 16:37:50 -0700[diff] [blame]105CONFIG_ERRNO_STR=y