| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: NVIDIA Tegra SOR Output Encoder |
| 8 | |
| 9 | maintainers: |
| 10 | - Thierry Reding <thierry.reding@gmail.com> |
| 11 | - Jon Hunter <jonathanh@nvidia.com> |
| 12 | |
| 13 | description: | |
| 14 | The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP |
| 15 | and DP outputs. |
| 16 | |
| 17 | properties: |
| 18 | $nodename: |
| 19 | pattern: "^sor@[0-9a-f]+$" |
| 20 | |
| 21 | compatible: |
| 22 | oneOf: |
| 23 | - enum: |
| 24 | - nvidia,tegra124-sor |
| 25 | - nvidia,tegra210-sor |
| 26 | - nvidia,tegra210-sor1 |
| 27 | - nvidia,tegra186-sor |
| 28 | - nvidia,tegra186-sor1 |
| 29 | - nvidia,tegra194-sor |
| 30 | |
| 31 | - items: |
| 32 | - const: nvidia,tegra132-sor |
| 33 | - const: nvidia,tegra124-sor |
| 34 | |
| 35 | reg: |
| 36 | maxItems: 1 |
| 37 | |
| 38 | interrupts: |
| 39 | maxItems: 1 |
| 40 | |
| 41 | clocks: |
| 42 | minItems: 5 |
| 43 | maxItems: 6 |
| 44 | |
| 45 | clock-names: |
| 46 | minItems: 5 |
| 47 | maxItems: 6 |
| 48 | |
| 49 | resets: |
| 50 | items: |
| 51 | - description: module reset |
| 52 | |
| 53 | reset-names: |
| 54 | items: |
| 55 | - const: sor |
| 56 | |
| 57 | power-domains: |
| 58 | maxItems: 1 |
| 59 | |
| 60 | avdd-io-hdmi-dp-supply: |
| 61 | description: I/O supply for HDMI/DP |
| 62 | |
| 63 | vdd-hdmi-dp-pll-supply: |
| 64 | description: PLL supply for HDMI/DP |
| 65 | |
| 66 | hdmi-supply: |
| 67 | description: +5.0V HDMI connector supply, required for HDMI |
| 68 | |
| 69 | # Tegra186 and later |
| 70 | nvidia,interface: |
| 71 | description: index of the SOR interface |
| 72 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 73 | |
| 74 | nvidia,ddc-i2c-bus: |
| 75 | description: phandle of an I2C controller used for DDC EDID |
| 76 | probing |
| 77 | $ref: /schemas/types.yaml#/definitions/phandle |
| 78 | |
| 79 | nvidia,hpd-gpio: |
| 80 | description: specifies a GPIO used for hotplug detection |
| 81 | maxItems: 1 |
| 82 | |
| 83 | nvidia,edid: |
| 84 | description: supplies a binary EDID blob |
| 85 | $ref: /schemas/types.yaml#/definitions/uint8-array |
| 86 | |
| 87 | nvidia,panel: |
| 88 | description: phandle of a display panel, required for eDP |
| 89 | $ref: /schemas/types.yaml#/definitions/phandle |
| 90 | |
| 91 | nvidia,xbar-cfg: |
| 92 | description: 5 cells containing the crossbar configuration. |
| 93 | Each lane of the SOR, identified by the cell's index, is |
| 94 | mapped via the crossbar to the pad specified by the cell's |
| 95 | value. |
| 96 | $ref: /schemas/types.yaml#/definitions/uint32-array |
| 97 | |
| 98 | # optional when driving an eDP output |
| 99 | nvidia,dpaux: |
| 100 | description: phandle to a DisplayPort AUX interface |
| 101 | $ref: /schemas/types.yaml#/definitions/phandle |
| 102 | |
| 103 | allOf: |
| 104 | - if: |
| 105 | properties: |
| 106 | compatible: |
| 107 | contains: |
| 108 | enum: |
| 109 | - nvidia,tegra186-sor |
| 110 | - nvidia,tegra194-sor |
| 111 | then: |
| 112 | properties: |
| 113 | clocks: |
| 114 | items: |
| 115 | - description: clock input for the SOR hardware |
| 116 | - description: SOR output clock |
| 117 | - description: input for the pixel clock |
| 118 | - description: reference clock for the SOR clock |
| 119 | - description: safe reference clock for the SOR clock |
| 120 | during power up |
| 121 | - description: SOR pad output clock |
| 122 | |
| 123 | clock-names: |
| 124 | items: |
| 125 | - const: sor |
| 126 | - enum: |
| 127 | - source # deprecated |
| 128 | - out |
| 129 | - const: parent |
| 130 | - const: dp |
| 131 | - const: safe |
| 132 | - const: pad |
| 133 | else: |
| 134 | properties: |
| 135 | clocks: |
| 136 | items: |
| 137 | - description: clock input for the SOR hardware |
| 138 | - description: SOR output clock |
| 139 | - description: input for the pixel clock |
| 140 | - description: reference clock for the SOR clock |
| 141 | - description: safe reference clock for the SOR clock |
| 142 | during power up |
| 143 | |
| 144 | clock-names: |
| 145 | items: |
| 146 | - const: sor |
| 147 | - enum: |
| 148 | - source # deprecated |
| 149 | - out |
| 150 | - const: parent |
| 151 | - const: dp |
| 152 | - const: safe |
| 153 | |
| 154 | additionalProperties: false |
| 155 | |
| 156 | required: |
| 157 | - compatible |
| 158 | - reg |
| 159 | - interrupts |
| 160 | - clocks |
| 161 | - clock-names |
| 162 | - resets |
| 163 | - reset-names |
| 164 | - avdd-io-hdmi-dp-supply |
| 165 | - vdd-hdmi-dp-pll-supply |
| 166 | |
| 167 | examples: |
| 168 | - | |
| 169 | #include <dt-bindings/clock/tegra210-car.h> |
| 170 | #include <dt-bindings/gpio/tegra-gpio.h> |
| 171 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 172 | |
| 173 | sor0: sor@54540000 { |
| 174 | compatible = "nvidia,tegra210-sor"; |
| 175 | reg = <0x54540000 0x00040000>; |
| 176 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 177 | clocks = <&tegra_car TEGRA210_CLK_SOR0>, |
| 178 | <&tegra_car TEGRA210_CLK_SOR0_OUT>, |
| 179 | <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, |
| 180 | <&tegra_car TEGRA210_CLK_PLL_DP>, |
| 181 | <&tegra_car TEGRA210_CLK_SOR_SAFE>; |
| 182 | clock-names = "sor", "out", "parent", "dp", "safe"; |
| 183 | resets = <&tegra_car 182>; |
| 184 | reset-names = "sor"; |
| 185 | pinctrl-0 = <&state_dpaux_aux>; |
| 186 | pinctrl-1 = <&state_dpaux_i2c>; |
| 187 | pinctrl-2 = <&state_dpaux_off>; |
| 188 | pinctrl-names = "aux", "i2c", "off"; |
| 189 | power-domains = <&pd_sor>; |
| 190 | |
| 191 | avdd-io-hdmi-dp-supply = <&avdd_1v05>; |
| 192 | vdd-hdmi-dp-pll-supply = <&vdd_1v8>; |
| 193 | hdmi-supply = <&vdd_hdmi>; |
| 194 | |
| 195 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 196 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) GPIO_ACTIVE_LOW>; |
| 197 | }; |