Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 65371c8ddff8e8d3af0719e489a08ebd06476726 / . / board / armadeus / apf27 / lowlevel_init.S
blob: 2f795e460aa16a282529d763dcfc30c7b5cfd39f [file] [log] [blame]
trem0053e3c2013-09-10 22:08:39 +0200[diff] [blame]1/*
2 * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <config.h>
8#include <generated/asm-offsets.h>
trem0053e3c2013-09-10 22:08:39 +0200[diff] [blame]9#include <asm/macro.h>
10#include <asm/arch/imx-regs.h>
11#include "apf27.h"
12
13 .macro init_aipi
14 /*
15 * setup AIPI1 and AIPI2
16 */
17 write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL
18 write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL
19 write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL
20 write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL
21
22 /* Change SDRAM signal strengh */
23 ldr r0, =GPCR
24 ldr r1, =ACFG_GPCR_VAL
25 ldr r5, [r0]
26 orr r5, r5, r1
27 str r5, [r0]
28
29 .endm /* init_aipi */
30
31 .macro init_clock
32 ldr r0, =CSCR
33 /* disable MPLL/SPLL first */
34 ldr r1, [r0]
35 bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
36 str r1, [r0]
37
38 /*
39 * pll clock initialization predefined in apf27.h
40 */
41 write32 MPCTL0, ACFG_MPCTL0_VAL
42 write32 SPCTL0, ACFG_SPCTL0_VAL
43
44 write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
45
46 /*
47 * add some delay here
48 */
49 mov r1, #0x1000
50 1: subs r1, r1, #0x1
51 bne 1b
52
53 /* peripheral clock divider */
54 write32 PCDR0, ACFG_PCDR0_VAL
55 write32 PCDR1, ACFG_PCDR1_VAL
56
57 /* Configure PCCR0 and PCCR1 */
58 write32 PCCR0, ACFG_PCCR0_VAL
59 write32 PCCR1, ACFG_PCCR1_VAL
60
61 .endm /* init_clock */
62
63 .macro init_ddr
64 /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
65 ldr r0, =IMX_ESD_BASE
66 ldr r4, =ESDMISC_SDRAM_RDY
672: ldr r1, [r0, #ESDMISC_ROF]
68 ands r1, r1, r4
69 bpl 2b
70
71 /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
72 ldr r0, =IMX_ESD_BASE
73 ldr r4, =ACFG_ESDMISC_VAL
74 orr r1, r4, #ESDMISC_MDDR_DL_RST
75 str r1, [r0, #ESDMISC_ROF]
76
77 /* Hold for more than 200ns */
78 ldr r1, =0x10000
791: subs r1, r1, #0x1
80 bne 1b
81
82 str r4, [r0]
83
84 ldr r0, =IMX_ESD_BASE
85 ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
86 str r1, [r0, #ESDCFG0_ROF]
87
88 ldr r0, =IMX_ESD_BASE
89 ldr r1, =ACFG_PRECHARGE_CMD
90 str r1, [r0, #ESDCTL0_ROF]
91
92 /* write8(0xA0001000, any value) */
93 ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
94 strb r2, [r1]
95
96 ldr r1, =ACFG_AUTOREFRESH_CMD
97 str r1, [r0, #ESDCTL0_ROF]
98
99 ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
100
101 ldr r6,=0x7 /* load loop counter */
1021: str r5,[r4] /* run auto-refresh cycle to array 0 */
103 subs r6,r6,#1
104 bne 1b
105
106 ldr r1, =ACFG_SET_MODE_REG_CMD
107 str r1, [r0, #ESDCTL0_ROF]
108
109 /* set standard mode register */
110 ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
111 strb r2, [r4]
112
113 /* set extended mode register */
114 ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
115 strb r5, [r4]
116
117 ldr r1, =ACFG_NORMAL_RW_CMD
118 str r1, [r0, #ESDCTL0_ROF]
119
120 /* 2nd sdram */
121 ldr r0, =IMX_ESD_BASE
122 ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
123 str r1, [r0, #ESDCFG1_ROF]
124
125 ldr r0, =IMX_ESD_BASE
126 ldr r1, =ACFG_PRECHARGE_CMD
127 str r1, [r0, #ESDCTL1_ROF]
128
129 /* write8(0xB0001000, any value) */
130 ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
131 strb r2, [r1]
132
133 ldr r1, =ACFG_AUTOREFRESH_CMD
134 str r1, [r0, #ESDCTL1_ROF]
135
136 ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
137
138 ldr r6,=0x7 /* load loop counter */
1391: str r5,[r4] /* run auto-refresh cycle to array 0 */
140 subs r6,r6,#1
141 bne 1b
142
143 ldr r1, =ACFG_SET_MODE_REG_CMD
144 str r1, [r0, #ESDCTL1_ROF]
145
146 /* set standard mode register */
147 ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
148 strb r2, [r4]
149
150 /* set extended mode register */
151 ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
152 strb r2, [r4]
153
154 ldr r1, =ACFG_NORMAL_RW_CMD
155 str r1, [r0, #ESDCTL1_ROF]
156 .endm /* init_ddr */
157
158.globl lowlevel_init
159lowlevel_init:
160
161 init_aipi
162 init_clock
163#ifdef CONFIG_SPL_BUILD
164 init_ddr
165#endif
166
167 mov pc, lr