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wdenk7e920de2004-06-09 12:47:02 +00001/*
2 * (C) Copyright 2004
3 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk7e920de2004-06-09 12:47:02 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
Wolfgang Denka1be4762008-05-20 16:00:29 +020020#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
wdenk7e920de2004-06-09 12:47:02 +000021#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */
22#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
23#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
24#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
25
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020026#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
27
wdenk7e920de2004-06-09 12:47:02 +000028/*
29 * OS Bootstrap configuration
30 *
31 */
32
33#if 0
34#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
35#else
36#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
37#endif
38
39#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
40
41#if 1
42#undef CONFIG_BOOTARGS
43#define CONFIG_BOOTCOMMAND \
44 "setenv bootargs console=ttyS0,38400 debug " \
45 "root=/dev/ram rw ramdisk_size=4096 " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010046 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk7e920de2004-06-09 12:47:02 +000047 "bootm ff800000 ff900000"
48#endif
49
50#if 0
51#undef CONFIG_BOOTARGS
52#define CONFIG_BOOTCOMMAND \
53 "bootp; " \
54 "setenv bootargs console=ttyS0,38400 debug " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010055 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
56 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk7e920de2004-06-09 12:47:02 +000057 "bootm"
58#endif
59
60/*
Jon Loeligerdcf14512007-07-09 21:48:26 -050061 * BOOTP options
wdenk7e920de2004-06-09 12:47:02 +000062 */
Jon Loeligerdcf14512007-07-09 21:48:26 -050063#define CONFIG_BOOTP_SUBNETMASK
64#define CONFIG_BOOTP_GATEWAY
65#define CONFIG_BOOTP_HOSTNAME
66#define CONFIG_BOOTP_BOOTPATH
67#define CONFIG_BOOTP_BOOTFILESIZE
68#define CONFIG_BOOTP_DNS2
69
Jon Loeliger37ec35e2007-07-04 22:31:56 -050070
wdenk7e920de2004-06-09 12:47:02 +000071/*
Jon Loeliger37ec35e2007-07-04 22:31:56 -050072 * Command line configuration.
wdenk7e920de2004-06-09 12:47:02 +000073 */
Jon Loeliger37ec35e2007-07-04 22:31:56 -050074#include <config_cmd_default.h>
wdenk7e920de2004-06-09 12:47:02 +000075
Jon Loeliger37ec35e2007-07-04 22:31:56 -050076#define CONFIG_CMD_ASKENV
77#define CONFIG_CMD_BEDBUG
78#define CONFIG_CMD_ELF
79#define CONFIG_CMD_IRQ
80#define CONFIG_CMD_I2C
81#define CONFIG_CMD_PCI
82#define CONFIG_CMD_DATE
83#define CONFIG_CMD_MII
84#define CONFIG_CMD_PING
85#define CONFIG_CMD_DHCP
86
wdenk7e920de2004-06-09 12:47:02 +000087/*
88 * Serial download configuration
89 *
90 */
91#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk7e920de2004-06-09 12:47:02 +000093
94/*
95 * KGDB Configuration
96 *
97 */
Jon Loeliger37ec35e2007-07-04 22:31:56 -050098#if defined(CONFIG_CMD_KGDB)
wdenk7e920de2004-06-09 12:47:02 +000099#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk7e920de2004-06-09 12:47:02 +0000100#endif
101
102/*
103 * Miscellaneous configurable options
104 *
105 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
wdenk7e920de2004-06-09 12:47:02 +0000107
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger37ec35e2007-07-04 22:31:56 -0500109#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk7e920de2004-06-09 12:47:02 +0000111#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk7e920de2004-06-09 12:47:02 +0000113#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200114#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
115#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
116#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk7e920de2004-06-09 12:47:02 +0000117
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200118#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
119#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk7e920de2004-06-09 12:47:02 +0000120
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200121#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
122#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk7e920de2004-06-09 12:47:02 +0000123
124/*
125 * For booting Linux, the board info and command line data
126 * have to be in the first 8 MB of memory, since this is
127 * the maximum mapped by the Linux kernel during initialization.
128 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk7e920de2004-06-09 12:47:02 +0000130
131/*
132 * watchdog configuration
133 *
134 */
135#undef CONFIG_WATCHDOG /* watchdog disabled */
136
137/*
138 * UART configuration
139 *
140 */
Stefan Roese3ddce572010-09-20 16:05:31 +0200141#define CONFIG_CONS_INDEX 1 /* Use UART0 */
142#define CONFIG_SYS_NS16550
143#define CONFIG_SYS_NS16550_SERIAL
144#define CONFIG_SYS_NS16550_REG_SIZE 1
145#define CONFIG_SYS_NS16550_CLK get_serial_clock()
146
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* use internal serial clock */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148#define CONFIG_SYS_BASE_BAUD 691200
wdenk7e920de2004-06-09 12:47:02 +0000149#define CONFIG_BAUDRATE 38400 /* Default baud rate */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk7e920de2004-06-09 12:47:02 +0000151 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
152
153/*
154 * I2C configuration
155 *
156 */
Dirk Eibach42b204f2013-04-25 02:40:01 +0000157#define CONFIG_SYS_I2C
158#define CONFIG_SYS_I2C_PPC4XX
159#define CONFIG_SYS_I2C_PPC4XX_CH0
160#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
161#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* I2C slave address */
wdenk7e920de2004-06-09 12:47:02 +0000162
163/*
164 * MII PHY configuration
165 *
166 */
Ben Warren3a918a62008-10-27 23:50:15 -0700167#define CONFIG_PPC4xx_EMAC
wdenk7e920de2004-06-09 12:47:02 +0000168#define CONFIG_MII 1 /* MII PHY management */
169#define CONFIG_PHY_ADDR 0 /* PHY address */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200170#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
wdenk7e920de2004-06-09 12:47:02 +0000171 /* 32usec min. for LXT971A */
172#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
173
174/*
175 * RTC configuration
176 *
177 * Note that DS1307 RTC is limited to 100Khz I2C bus.
178 *
179 */
180#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
181
182/*
183 * PCI stuff
184 *
185 */
186#define CONFIG_PCI /* include pci support */
Gabor Juhosb4458732013-05-30 07:06:12 +0000187#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenk7e920de2004-06-09 12:47:02 +0000188#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
189#define PCI_HOST_FORCE 1 /* configure as pci host */
190#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
191
192#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
193#define CONFIG_PCI_PNP /* do pci plug-and-play */
194 /* resource configuration */
195#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
196#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
197
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
199#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
200#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
201#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
202#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
203#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
204#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
205#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenk7e920de2004-06-09 12:47:02 +0000206
207/*
208 * IDE stuff
209 *
210 */
211#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
212#undef CONFIG_IDE_LED /* no led for ide supported */
213#undef CONFIG_IDE_RESET /* no reset for ide supported */
214
215/*
216 * Environment configuration
217 *
218 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200219#define CONFIG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
Jean-Christophe PLAGNIOL-VILLARDfdb79c32008-09-10 22:47:59 +0200220#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200221#undef CONFIG_ENV_IS_IN_EEPROM
wdenk7e920de2004-06-09 12:47:02 +0000222
223/*
224 * General Memory organization
225 *
226 * Start addresses for the final memory configuration
227 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk7e920de2004-06-09 12:47:02 +0000229 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200230#define CONFIG_SYS_SDRAM_BASE 0x00000000
231#define CONFIG_SYS_FLASH_BASE 0xFF800000
232#define CONFIG_SYS_FLASH_SIZE 0x00800000
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200233#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200234#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
235#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
wdenk7e920de2004-06-09 12:47:02 +0000236
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200237#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
238#define CONFIG_SYS_RAMSTART
wdenk7e920de2004-06-09 12:47:02 +0000239#endif
240
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200241#if defined(CONFIG_ENV_IS_IN_FLASH)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200242#define CONFIG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
243#define CONFIG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
244#define CONFIG_ENV_SIZE 0x00001000 /* Size of Environment */
245#define CONFIG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
wdenk7e920de2004-06-09 12:47:02 +0000246#endif
247
248/*
249 * FLASH Device configuration
250 *
251 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200252#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200253#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200254#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
255#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
256#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
257#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max # of sectors on one chip */
258#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
259#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
wdenk7e920de2004-06-09 12:47:02 +0000260
261/*
262 * On Chip Memory location/size
263 *
264 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
266#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenk7e920de2004-06-09 12:47:02 +0000267
268/*
269 * Global info and initial stack
270 *
271 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200272#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200273#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200274#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200275#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk7e920de2004-06-09 12:47:02 +0000276
277/*
wdenk7e920de2004-06-09 12:47:02 +0000278 * Miscellaneous board specific definitions
279 *
280 */
281#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */
282
wdenk7e920de2004-06-09 12:47:02 +0000283#endif /* __CONFIG_H */