blob: 1ab2b3d51a2caa60bb0e811865b94190c73e0ebf [file] [log] [blame]
Andre Schwarz2a293292008-07-09 18:30:44 +02001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2008
6 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
7 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
Andre Schwarz2a293292008-07-09 18:30:44 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#include <version.h>
15
Andre Schwarz2a293292008-07-09 18:30:44 +020016#define CONFIG_MPC5200 1
17
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020018#ifndef CONFIG_SYS_TEXT_BASE
19#define CONFIG_SYS_TEXT_BASE 0xFF800000
20#endif
21
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020022#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
Andre Schwarz2a293292008-07-09 18:30:44 +020023
Andre Schwarz2a293292008-07-09 18:30:44 +020024#define CONFIG_MISC_INIT_R 1
25
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020026#define CONFIG_SYS_CACHELINE_SIZE 32
Wolfgang Denkec1067c2008-08-12 14:54:04 +020027#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020028#define CONFIG_SYS_CACHELINE_SHIFT 5
Andre Schwarz2a293292008-07-09 18:30:44 +020029#endif
30
31#define CONFIG_PSC_CONSOLE 1
32#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020033#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
Andre Schwarz2a293292008-07-09 18:30:44 +020034
35#define CONFIG_PCI 1
36#define CONFIG_PCI_PNP 1
37#undef CONFIG_PCI_SCAN_SHOW
38#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
39
40#define CONFIG_PCI_MEM_BUS 0x40000000
41#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
42#define CONFIG_PCI_MEM_SIZE 0x10000000
43
44#define CONFIG_PCI_IO_BUS 0x50000000
45#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
46#define CONFIG_PCI_IO_SIZE 0x01000000
47
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020048#define CONFIG_SYS_XLB_PIPELINING 1
Andre Schwarz2a293292008-07-09 18:30:44 +020049#define CONFIG_HIGH_BATS 1
50
51#define MV_CI mvBlueCOUGAR-P
52#define MV_VCI mvBlueCOUGAR-P
53#define MV_FPGA_DATA 0xff860000
André Schwarza8e1d952009-08-27 14:48:35 +020054#define MV_FPGA_SIZE 0
André Schwarz901f5982009-07-17 14:50:24 +020055#define MV_KERNEL_ADDR 0xffd00000
Andre Schwarz2a293292008-07-09 18:30:44 +020056#define MV_INITRD_ADDR 0xff900000
André Schwarz901f5982009-07-17 14:50:24 +020057#define MV_INITRD_LENGTH 0x00400000
Andre Schwarz2a293292008-07-09 18:30:44 +020058#define MV_SCRATCH_ADDR 0x00000000
59#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
Peter Tyserd78876c2009-09-16 21:38:10 -050060#define MV_SCRIPT_ADDR 0xff840000
61#define MV_SCRIPT_ADDR2 0xff850000
Andre Schwarz2a293292008-07-09 18:30:44 +020062#define MV_DTB_ADDR 0xfffc0000
63
64#define CONFIG_SHOW_BOOT_PROGRESS 1
65
66#define MV_KERNEL_ADDR_RAM 0x00100000
67#define MV_DTB_ADDR_RAM 0x00600000
68#define MV_INITRD_ADDR_RAM 0x01000000
69
70/* pass open firmware flat tree */
71#define CONFIG_OF_LIBFDT 1
72#define CONFIG_OF_BOARD_SETUP 1
73
74#define OF_CPU "PowerPC,5200@0"
75#define OF_SOC "soc5200@f0000000"
76#define OF_TBCLK (bd->bi_busfreq / 4)
77#define MV_DTB_NAME mvbc-p.dtb
78#define CONFIG_OF_STDOUT_VIA_ALIAS 1
79
80/*
81 * Supported commands
82 */
83#include <config_cmd_default.h>
84
85#define CONFIG_CMD_CACHE
86#define CONFIG_CMD_NET
87#define CONFIG_CMD_PING
88#define CONFIG_CMD_DHCP
89#define CONFIG_CMD_SDRAM
90#define CONFIG_CMD_PCI
91#define CONFIG_CMD_FPGA
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +053092#define CONFIG_CMD_FPGA_LOADMK
André Schwarz901f5982009-07-17 14:50:24 +020093#define CONFIG_CMD_I2C
Andre Schwarz2a293292008-07-09 18:30:44 +020094
95#undef CONFIG_WATCHDOG
96
97#define CONFIG_BOOTP_VENDOREX
98#define CONFIG_BOOTP_SUBNETMASK
99#define CONFIG_BOOTP_GATEWAY
100#define CONFIG_BOOTP_DNS
101#define CONFIG_BOOTP_DNS2
102#define CONFIG_BOOTP_HOSTNAME
103#define CONFIG_BOOTP_BOOTFILESIZE
104#define CONFIG_BOOTP_BOOTPATH
105#define CONFIG_BOOTP_NTPSERVER
106#define CONFIG_BOOTP_RANDOM_DELAY
107#define CONFIG_BOOTP_SEND_HOSTNAME
Przemyslaw Marczakcd9c2682014-03-25 10:58:19 +0100108#define CONFIG_LIB_RAND
Andre Schwarz2a293292008-07-09 18:30:44 +0200109
110/*
111 * Autoboot
112 */
113#define CONFIG_BOOTDELAY 2
114#define CONFIG_AUTOBOOT_KEYED
115#define CONFIG_AUTOBOOT_STOP_STR "s"
116#define CONFIG_ZERO_BOOTDELAY_CHECK
117#define CONFIG_RESET_TO_RETRY 1000
118
Peter Tyserd78876c2009-09-16 21:38:10 -0500119#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
120 then source ${script_addr}; \
121 else source ${script_addr2}; \
Andre Schwarz2a293292008-07-09 18:30:44 +0200122 fi;"
123
124#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
125#define CONFIG_ENV_OVERWRITE
126
Andre Schwarz2a293292008-07-09 18:30:44 +0200127#define CONFIG_EXTRA_ENV_SETTINGS \
128 "console_nr=0\0" \
129 "console=yes\0" \
130 "stdin=serial\0" \
131 "stdout=serial\0" \
132 "stderr=serial\0" \
133 "fpga=0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200134 "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
135 "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
136 "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
137 "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
138 "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
139 "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
140 "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
141 "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
142 "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
143 "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
144 "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
145 "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
146 "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
147 "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
Andre Schwarz2a293292008-07-09 18:30:44 +0200148 "mv_version=" U_BOOT_VERSION "\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200149 "dhcp_client_id=" __stringify(MV_CI) "\0" \
150 "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
Andre Schwarz2a293292008-07-09 18:30:44 +0200151 "netretry=no\0" \
152 "use_static_ipaddr=no\0" \
153 "static_ipaddr=192.168.90.10\0" \
154 "static_netmask=255.255.255.0\0" \
155 "static_gateway=0.0.0.0\0" \
156 "initrd_name=uInitrd.mvbc-p-rfs\0" \
157 "zcip=no\0" \
158 "netboot=yes\0" \
159 "mvtest=Ff\0" \
160 "tried_bootfromflash=no\0" \
161 "tried_bootfromnet=no\0" \
162 "use_dhcp=yes\0" \
163 "gev_start=yes\0" \
164 "mvbcdma_debug=0\0" \
165 "mvbcia_debug=0\0" \
166 "propdev_debug=0\0" \
167 "gevss_debug=0\0" \
168 "watchdog=1\0" \
André Schwarz901f5982009-07-17 14:50:24 +0200169 "sensor_cnt=1\0" \
Andre Schwarz2a293292008-07-09 18:30:44 +0200170 ""
171
Andre Schwarz2a293292008-07-09 18:30:44 +0200172/*
173 * IPB Bus clocking configuration.
174 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
176#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
Andre Schwarz2a293292008-07-09 18:30:44 +0200177
178/*
179 * Flash configuration
180 */
181#undef CONFIG_FLASH_16BIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200183#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
185#define CONFIG_SYS_FLASH_EMPTY_INFO
Andre Schwarz2a293292008-07-09 18:30:44 +0200186
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200187#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
188#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
Andre Schwarz2a293292008-07-09 18:30:44 +0200189
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_MAX_FLASH_BANKS 1
191#define CONFIG_SYS_MAX_FLASH_SECT 256
Andre Schwarz2a293292008-07-09 18:30:44 +0200192
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_LOWBOOT
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200194#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_FLASH_SIZE 0x00800000
Andre Schwarz2a293292008-07-09 18:30:44 +0200196
197/*
198 * Environment settings
199 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200200#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#undef CONFIG_SYS_FLASH_PROTECTION
Andre Schwarz2a293292008-07-09 18:30:44 +0200202
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200203#define CONFIG_ENV_ADDR 0xFFFE0000
204#define CONFIG_ENV_SIZE 0x10000
205#define CONFIG_ENV_SECT_SIZE 0x10000
206#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
207#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Andre Schwarz2a293292008-07-09 18:30:44 +0200208
209/*
210 * Memory map
211 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_MBAR 0xF0000000
213#define CONFIG_SYS_SDRAM_BASE 0x00000000
214#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Andre Schwarz2a293292008-07-09 18:30:44 +0200215
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200217#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Andre Schwarz2a293292008-07-09 18:30:44 +0200218
Wolfgang Denk0191e472010-10-26 14:34:52 +0200219#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200220#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andre Schwarz2a293292008-07-09 18:30:44 +0200221
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200222#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
224#define CONFIG_SYS_RAMBOOT 1
Andre Schwarz2a293292008-07-09 18:30:44 +0200225#endif
226
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200227/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
228#define CONFIG_SYS_MONITOR_LEN (512 << 10)
229#define CONFIG_SYS_MALLOC_LEN (512 << 10)
230#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
Andre Schwarz2a293292008-07-09 18:30:44 +0200231
232/*
André Schwarz901f5982009-07-17 14:50:24 +0200233 * I2C configuration
234 */
235#define CONFIG_HARD_I2C 1
236#define CONFIG_SYS_I2C_MODULE 1
237#define CONFIG_SYS_I2C_SPEED 86000
238#define CONFIG_SYS_I2C_SLAVE 0x7F
239
240/*
Andre Schwarz2a293292008-07-09 18:30:44 +0200241 * Ethernet configuration
242 */
Andre Schwarz2a293292008-07-09 18:30:44 +0200243#define CONFIG_NET_RETRY_COUNT 5
244
245#define CONFIG_E1000
Wolfgang Denk9a0882b2008-07-31 13:57:20 +0200246#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
Andre Schwarz2a293292008-07-09 18:30:44 +0200247#undef CONFIG_MPC5xxx_FEC
248#undef CONFIG_PHY_ADDR
249#define CONFIG_NETDEV eth0
250
251/*
252 * Miscellaneous configurable options
253 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200254#define CONFIG_SYS_HUSH_PARSER
Andre Schwarz2a293292008-07-09 18:30:44 +0200255#define CONFIG_CMDLINE_EDITING
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200256#undef CONFIG_SYS_LONGHELP
Wolfgang Denkec1067c2008-08-12 14:54:04 +0200257#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200258#define CONFIG_SYS_CBSIZE 1024
Andre Schwarz2a293292008-07-09 18:30:44 +0200259#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200260#define CONFIG_SYS_CBSIZE 256
Andre Schwarz2a293292008-07-09 18:30:44 +0200261#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200262#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
263#define CONFIG_SYS_MAXARGS 16
264#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Andre Schwarz2a293292008-07-09 18:30:44 +0200265
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200266#define CONFIG_SYS_MEMTEST_START 0x00800000
267#define CONFIG_SYS_MEMTEST_END 0x02f00000
Andre Schwarz2a293292008-07-09 18:30:44 +0200268
Andre Schwarz2a293292008-07-09 18:30:44 +0200269/* default load address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200270#define CONFIG_SYS_LOAD_ADDR 0x02000000
Andre Schwarz2a293292008-07-09 18:30:44 +0200271/* default location for tftp and bootm */
272#define CONFIG_LOADADDR 0x00200000
273
274/*
275 * Various low-level settings
276 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200277#define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004
Andre Schwarz2a293292008-07-09 18:30:44 +0200278
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200279#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
280#define CONFIG_SYS_HID0_FINAL HID0_ICE
Andre Schwarz2a293292008-07-09 18:30:44 +0200281
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200282#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
283#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
284#define CONFIG_SYS_BOOTCS_CFG 0x00047800
285#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
286#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Andre Schwarz2a293292008-07-09 18:30:44 +0200287
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200288#define CONFIG_SYS_CS_BURST 0x000000f0
289#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
Andre Schwarz2a293292008-07-09 18:30:44 +0200290
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200291#define CONFIG_SYS_RESET_ADDRESS 0x00000100
Andre Schwarz2a293292008-07-09 18:30:44 +0200292
293#undef FPGA_DEBUG
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200294#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
Michal Simekb6b8aaa2013-05-01 18:05:56 +0200295#define CONFIG_FPGA
Andre Schwarz2a293292008-07-09 18:30:44 +0200296#define CONFIG_FPGA_ALTERA 1
297#define CONFIG_FPGA_CYCLON2 1
298#define CONFIG_FPGA_COUNT 1
299
300#endif