blob: 46ed64655a8778a0b78042181ee1a50a34921963 [file] [log] [blame]
Benjamin Gaignard77611122018-11-27 13:49:52 +01001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
Patrick Delaunayecd1bac2020-11-06 19:01:39 +01006#define LOG_CATEGORY UCLASS_HWSPINLOCK
7
Benjamin Gaignard77611122018-11-27 13:49:52 +01008#include <common.h>
9#include <clk.h>
10#include <dm.h>
11#include <hwspinlock.h>
Simon Glass9bc15642020-02-03 07:36:16 -070012#include <malloc.h>
Benjamin Gaignard77611122018-11-27 13:49:52 +010013#include <asm/io.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060014#include <linux/bitops.h>
Benjamin Gaignard77611122018-11-27 13:49:52 +010015
16#define STM32_MUTEX_COREID BIT(8)
17#define STM32_MUTEX_LOCK_BIT BIT(31)
18#define STM32_MUTEX_NUM_LOCKS 32
19
20struct stm32mp1_hws_priv {
21 fdt_addr_t base;
22};
23
24static int stm32mp1_lock(struct udevice *dev, int index)
25{
26 struct stm32mp1_hws_priv *priv = dev_get_priv(dev);
27 u32 status;
28
29 if (index >= STM32_MUTEX_NUM_LOCKS)
30 return -EINVAL;
31
32 status = readl(priv->base + index * sizeof(u32));
33 if (status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID))
34 return -EBUSY;
35
36 writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID,
37 priv->base + index * sizeof(u32));
38
39 status = readl(priv->base + index * sizeof(u32));
40 if (status != (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID))
41 return -EINVAL;
42
43 return 0;
44}
45
46static int stm32mp1_unlock(struct udevice *dev, int index)
47{
48 struct stm32mp1_hws_priv *priv = dev_get_priv(dev);
49
50 if (index >= STM32_MUTEX_NUM_LOCKS)
51 return -EINVAL;
52
53 writel(STM32_MUTEX_COREID, priv->base + index * sizeof(u32));
54
55 return 0;
56}
57
58static int stm32mp1_hwspinlock_probe(struct udevice *dev)
59{
60 struct stm32mp1_hws_priv *priv = dev_get_priv(dev);
61 struct clk clk;
62 int ret;
63
64 priv->base = dev_read_addr(dev);
65 if (priv->base == FDT_ADDR_T_NONE)
66 return -EINVAL;
67
68 ret = clk_get_by_index(dev, 0, &clk);
69 if (ret)
70 return ret;
71
72 ret = clk_enable(&clk);
73 if (ret)
74 clk_free(&clk);
75
76 return ret;
77}
78
79static const struct hwspinlock_ops stm32mp1_hwspinlock_ops = {
80 .lock = stm32mp1_lock,
81 .unlock = stm32mp1_unlock,
82};
83
84static const struct udevice_id stm32mp1_hwspinlock_ids[] = {
85 { .compatible = "st,stm32-hwspinlock" },
86 {}
87};
88
89U_BOOT_DRIVER(hwspinlock_stm32mp1) = {
90 .name = "hwspinlock_stm32mp1",
91 .id = UCLASS_HWSPINLOCK,
92 .of_match = stm32mp1_hwspinlock_ids,
93 .ops = &stm32mp1_hwspinlock_ops,
94 .probe = stm32mp1_hwspinlock_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -070095 .priv_auto = sizeof(struct stm32mp1_hws_priv),
Benjamin Gaignard77611122018-11-27 13:49:52 +010096};