Patrick Delaunay | c5c9069 | 2019-11-06 16:16:32 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR X11 |
Michael Kurz | bccef71 | 2017-01-22 16:04:23 +0100 | [diff] [blame] | 2 | /* |
Patrice Chotard | 24dffa5 | 2019-02-19 16:49:05 +0100 | [diff] [blame] | 3 | * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com> |
Michael Kurz | bccef71 | 2017-01-22 16:04:23 +0100 | [diff] [blame] | 4 | * |
Michael Kurz | bccef71 | 2017-01-22 16:04:23 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include "stm32f746.dtsi" |
Patrice Chotard | 24dffa5 | 2019-02-19 16:49:05 +0100 | [diff] [blame] | 9 | #include "stm32f746-pinctrl.dtsi" |
Patrice Chotard | da8f8ef | 2018-08-06 09:38:18 +0200 | [diff] [blame] | 10 | #include <dt-bindings/gpio/gpio.h> |
Dario Binacchi | 2d89c64 | 2023-09-03 22:48:45 +0200 | [diff] [blame] | 11 | #include <dt-bindings/input/input.h> |
| 12 | #include <dt-bindings/interrupt-controller/irq.h> |
Michael Kurz | bccef71 | 2017-01-22 16:04:23 +0100 | [diff] [blame] | 13 | |
| 14 | / { |
| 15 | model = "STMicroelectronics STM32F746-DISCO board"; |
| 16 | compatible = "st,stm32f746-disco", "st,stm32f746"; |
| 17 | |
| 18 | chosen { |
Patrice Chotard | 24dffa5 | 2019-02-19 16:49:05 +0100 | [diff] [blame] | 19 | bootargs = "root=/dev/ram"; |
Michael Kurz | bccef71 | 2017-01-22 16:04:23 +0100 | [diff] [blame] | 20 | stdout-path = "serial0:115200n8"; |
| 21 | }; |
| 22 | |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 23 | memory@c0000000 { |
Patrick Delaunay | c5c9069 | 2019-11-06 16:16:32 +0100 | [diff] [blame] | 24 | device_type = "memory"; |
Michael Kurz | bccef71 | 2017-01-22 16:04:23 +0100 | [diff] [blame] | 25 | reg = <0xC0000000 0x800000>; |
| 26 | }; |
| 27 | |
| 28 | aliases { |
Vikas Manocha | da913d3 | 2017-02-12 10:25:47 -0800 | [diff] [blame] | 29 | serial0 = &usart1; |
Michael Kurz | bccef71 | 2017-01-22 16:04:23 +0100 | [diff] [blame] | 30 | }; |
Vikas Manocha | 9c7573e | 2017-04-10 15:03:00 -0700 | [diff] [blame] | 31 | |
Patrice Chotard | 24dffa5 | 2019-02-19 16:49:05 +0100 | [diff] [blame] | 32 | usbotg_hs_phy: usb-phy { |
| 33 | #phy-cells = <0>; |
| 34 | compatible = "usb-nop-xceiv"; |
| 35 | clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; |
| 36 | clock-names = "main_clk"; |
| 37 | }; |
| 38 | |
| 39 | /* This turns on vbus for otg fs for host mode (dwc2) */ |
| 40 | vcc5v_otg_fs: vcc5v-otg-fs-regulator { |
| 41 | compatible = "regulator-fixed"; |
| 42 | gpio = <&gpiod 5 0>; |
| 43 | regulator-name = "vcc5_host1"; |
| 44 | regulator-always-on; |
| 45 | }; |
| 46 | |
| 47 | mmc_vcard: mmc_vcard { |
| 48 | compatible = "regulator-fixed"; |
| 49 | regulator-name = "mmc_vcard"; |
| 50 | regulator-min-microvolt = <3300000>; |
| 51 | regulator-max-microvolt = <3300000>; |
| 52 | }; |
Michael Kurz | bccef71 | 2017-01-22 16:04:23 +0100 | [diff] [blame] | 53 | }; |
| 54 | |
Vikas Manocha | da913d3 | 2017-02-12 10:25:47 -0800 | [diff] [blame] | 55 | &clk_hse { |
| 56 | clock-frequency = <25000000>; |
| 57 | }; |
| 58 | |
Patrice Chotard | 24dffa5 | 2019-02-19 16:49:05 +0100 | [diff] [blame] | 59 | &i2c1 { |
| 60 | pinctrl-0 = <&i2c1_pins_b>; |
Vikas Manocha | 6ad568c | 2017-02-12 10:25:51 -0800 | [diff] [blame] | 61 | pinctrl-names = "default"; |
Patrice Chotard | 24dffa5 | 2019-02-19 16:49:05 +0100 | [diff] [blame] | 62 | i2c-scl-rising-time-ns = <185>; |
| 63 | i2c-scl-falling-time-ns = <20>; |
Vikas Manocha | 6ad568c | 2017-02-12 10:25:51 -0800 | [diff] [blame] | 64 | status = "okay"; |
Dario Binacchi | 2d89c64 | 2023-09-03 22:48:45 +0200 | [diff] [blame] | 65 | }; |
| 66 | |
| 67 | &i2c3 { |
| 68 | pinctrl-0 = <&i2c3_pins_a>; |
| 69 | pinctrl-names = "default"; |
| 70 | clock-frequency = <400000>; |
| 71 | status = "okay"; |
| 72 | |
| 73 | touchscreen@38 { |
| 74 | compatible = "edt,edt-ft5306"; |
| 75 | reg = <0x38>; |
| 76 | interrupt-parent = <&gpioi>; |
| 77 | interrupts = <13 IRQ_TYPE_EDGE_FALLING>; |
| 78 | touchscreen-size-x = <480>; |
| 79 | touchscreen-size-y = <272>; |
| 80 | }; |
Vikas Manocha | 6ad568c | 2017-02-12 10:25:51 -0800 | [diff] [blame] | 81 | }; |
| 82 | |
Patrice Chotard | 24dffa5 | 2019-02-19 16:49:05 +0100 | [diff] [blame] | 83 | &sdio1 { |
Patrice Chotard | 0d24b0d | 2017-12-12 10:14:59 +0100 | [diff] [blame] | 84 | status = "okay"; |
Patrice Chotard | 24dffa5 | 2019-02-19 16:49:05 +0100 | [diff] [blame] | 85 | vmmc-supply = <&mmc_vcard>; |
Patrice Chotard | da8f8ef | 2018-08-06 09:38:18 +0200 | [diff] [blame] | 86 | cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; |
Patrice Chotard | 0d24b0d | 2017-12-12 10:14:59 +0100 | [diff] [blame] | 87 | pinctrl-names = "default", "opendrain"; |
Patrice Chotard | 24dffa5 | 2019-02-19 16:49:05 +0100 | [diff] [blame] | 88 | pinctrl-0 = <&sdio_pins_a>; |
| 89 | pinctrl-1 = <&sdio_pins_od_a>; |
Patrice Chotard | 0d24b0d | 2017-12-12 10:14:59 +0100 | [diff] [blame] | 90 | bus-width = <4>; |
Patrice Chotard | 24dffa5 | 2019-02-19 16:49:05 +0100 | [diff] [blame] | 91 | }; |
| 92 | |
Patrice Chotard | 8397532 | 2022-09-23 13:20:33 +0200 | [diff] [blame] | 93 | &timers5 { |
| 94 | /* Override timer5 to act as clockevent */ |
| 95 | compatible = "st,stm32-timer"; |
| 96 | interrupts = <50>; |
| 97 | status = "okay"; |
| 98 | /delete-property/#address-cells; |
| 99 | /delete-property/#size-cells; |
| 100 | /delete-property/clock-names; |
| 101 | /delete-node/pwm; |
| 102 | /delete-node/timer@4; |
| 103 | }; |
| 104 | |
Patrice Chotard | 24dffa5 | 2019-02-19 16:49:05 +0100 | [diff] [blame] | 105 | &usart1 { |
| 106 | pinctrl-0 = <&usart1_pins_b>; |
| 107 | pinctrl-names = "default"; |
| 108 | status = "okay"; |
| 109 | }; |
| 110 | |
| 111 | &usbotg_fs { |
| 112 | dr_mode = "host"; |
| 113 | pinctrl-0 = <&usbotg_fs_pins_a>; |
| 114 | pinctrl-names = "default"; |
| 115 | status = "okay"; |
| 116 | }; |
| 117 | |
| 118 | &usbotg_hs { |
| 119 | dr_mode = "host"; |
| 120 | phys = <&usbotg_hs_phy>; |
| 121 | phy-names = "usb2-phy"; |
| 122 | pinctrl-0 = <&usbotg_hs_pins_b>; |
| 123 | pinctrl-names = "default"; |
| 124 | status = "okay"; |
Patrice Chotard | 0d24b0d | 2017-12-12 10:14:59 +0100 | [diff] [blame] | 125 | }; |