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git01.mediatek.com / filogic / uboot / 64c240898eb2316dc0d703d20330a33ad3042ca6 / . / arch / arm / dts / k3-am625-r5-sk.dts
blob: bf219226b974f03062439fc7b6ec7a5daec286b9 [file] [log] [blame]
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AM625 SK dts file for R5 SPL
4 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
7#include "k3-am625-sk.dts"
8#include "k3-am62x-sk-ddr4-1600MTs.dtsi"
9#include "k3-am62-ddr.dtsi"
10
11#include "k3-am625-sk-u-boot.dtsi"
12
13/ {
14 aliases {
15 remoteproc0 = &sysctrler;
16 remoteproc1 = &a53_0;
17 serial0 = &wkup_uart0;
18 serial3 = &main_uart1;
19 };
20
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]21 a53_0: a53@0 {
22 compatible = "ti,am654-rproc";
23 reg = <0x00 0x00a90000 0x00 0x10>;
24 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
Manorit Chawdhryf023d772023-04-14 09:47:59 +0530[diff] [blame]25 <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
26 <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]27 resets = <&k3_reset 135 0>;
28 clocks = <&k3_clks 61 0>;
29 assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
30 assigned-clock-parents = <&k3_clks 61 2>;
31 assigned-clock-rates = <200000000>, <1200000000>;
32 ti,sci = <&dmsc>;
33 ti,sci-proc-id = <32>;
34 ti,sci-host-id = <10>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]36 };
37
38 dm_tifs: dm-tifs {
39 compatible = "ti,j721e-dm-sci";
40 ti,host-id = <36>;
41 ti,secure-host;
42 mbox-names = "rx", "tx";
43 mboxes= <&secure_proxy_main 22>,
44 <&secure_proxy_main 23>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]46 };
47};
48
49&dmsc {
50 mboxes= <&secure_proxy_main 0>,
51 <&secure_proxy_main 1>,
52 <&secure_proxy_main 0>;
53 mbox-names = "rx", "tx", "notify";
54 ti,host-id = <35>;
55 ti,secure-host;
56};
57
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]58&mcu_esm {
59 bootph-pre-ram;
Julien Panisb9f6fb32022-07-01 14:30:10 +0200[diff] [blame]60};
61
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]62&secure_proxy_sa3 {
63 bootph-pre-ram;
64 /* We require this for boot handshake */
65 status = "okay";
66};
67
68&main_esm {
69 bootph-pre-ram;
70};
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]71
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]72&cbass_main {
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]73 sysctrler: sysctrler {
74 compatible = "ti,am654-system-controller";
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]75 mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]76 mbox-names = "tx", "rx", "boot_notify";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]78 };
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]79};
80
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]81&wkup_uart0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]83};
84
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]85&main_uart1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]87};
88
89/* WKUP UART0 is used for DM firmware logs */
90&wkup_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]92};
93
94/* Main UART1 is used for TIFS firmware logs */
95&main_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]97};
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]98
99&ospi0 {
100 reg = <0x00 0x0fc40000 0x00 0x100>,
101 <0x00 0x60000000 0x00 0x08000000>;
102};