Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Matthias Kaehlcke | 3b8d1a4 | 2010-01-31 17:39:49 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> |
| 4 | * |
| 5 | * Copyright (C) 2004, 2005 |
| 6 | * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com> |
Matthias Kaehlcke | 3b8d1a4 | 2010-01-31 17:39:49 +0100 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef _EP93XX_ETH_H |
| 10 | #define _EP93XX_ETH_H |
| 11 | |
| 12 | #include <net.h> |
| 13 | |
| 14 | /** |
| 15 | * #define this to dump device status and queue info during initialization and |
| 16 | * following errors. |
| 17 | */ |
| 18 | #undef EP93XX_MAC_DEBUG |
| 19 | |
| 20 | /** |
| 21 | * Number of descriptor and status entries in our RX queues. |
| 22 | * It must be power of 2 ! |
| 23 | */ |
| 24 | #define NUMRXDESC PKTBUFSRX |
| 25 | |
| 26 | /** |
| 27 | * Number of descriptor and status entries in our TX queues. |
| 28 | */ |
| 29 | #define NUMTXDESC 1 |
| 30 | |
| 31 | /** |
| 32 | * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT) |
| 33 | */ |
| 34 | #define TXSTARTMAX 944 |
| 35 | |
| 36 | /** |
| 37 | * Receive descriptor queue entry |
| 38 | */ |
| 39 | struct rx_descriptor { |
| 40 | uint32_t word1; |
| 41 | uint32_t word2; |
| 42 | }; |
| 43 | |
| 44 | /** |
| 45 | * Receive status queue entry |
| 46 | */ |
| 47 | struct rx_status { |
| 48 | uint32_t word1; |
| 49 | uint32_t word2; |
| 50 | }; |
| 51 | |
| 52 | #define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01) |
| 53 | #define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01) |
| 54 | #define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF) |
| 55 | |
| 56 | /** |
| 57 | * Transmit descriptor queue entry |
| 58 | */ |
| 59 | struct tx_descriptor { |
| 60 | uint32_t word1; |
| 61 | uint32_t word2; |
| 62 | }; |
| 63 | |
| 64 | #define TX_DESC_EOF (1 << 31) |
| 65 | |
| 66 | /** |
| 67 | * Transmit status queue entry |
| 68 | */ |
| 69 | struct tx_status { |
| 70 | uint32_t word1; |
| 71 | }; |
| 72 | |
| 73 | #define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01) |
| 74 | #define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01) |
| 75 | |
| 76 | /** |
| 77 | * Transmit descriptor queue |
| 78 | */ |
| 79 | struct tx_descriptor_queue { |
| 80 | struct tx_descriptor *base; |
| 81 | struct tx_descriptor *current; |
| 82 | struct tx_descriptor *end; |
| 83 | }; |
| 84 | |
| 85 | /** |
| 86 | * Transmit status queue |
| 87 | */ |
| 88 | struct tx_status_queue { |
| 89 | struct tx_status *base; |
| 90 | volatile struct tx_status *current; |
| 91 | struct tx_status *end; |
| 92 | }; |
| 93 | |
| 94 | /** |
| 95 | * Receive descriptor queue |
| 96 | */ |
| 97 | struct rx_descriptor_queue { |
| 98 | struct rx_descriptor *base; |
| 99 | struct rx_descriptor *current; |
| 100 | struct rx_descriptor *end; |
| 101 | }; |
| 102 | |
| 103 | /** |
| 104 | * Receive status queue |
| 105 | */ |
| 106 | struct rx_status_queue { |
| 107 | struct rx_status *base; |
| 108 | volatile struct rx_status *current; |
| 109 | struct rx_status *end; |
| 110 | }; |
| 111 | |
| 112 | /** |
| 113 | * EP93xx MAC private data structure |
| 114 | */ |
| 115 | struct ep93xx_priv { |
| 116 | struct rx_descriptor_queue rx_dq; |
| 117 | struct rx_status_queue rx_sq; |
| 118 | void *rx_buffer[NUMRXDESC]; |
| 119 | |
| 120 | struct tx_descriptor_queue tx_dq; |
| 121 | struct tx_status_queue tx_sq; |
| 122 | |
| 123 | struct mac_regs *regs; |
| 124 | }; |
| 125 | |
| 126 | #endif |