| wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 1 | JSE Configuration Details |
| 2 | |
| 3 | Memory Bank 0 -- Flash chip |
| 4 | --------------------------- |
| 5 | |
| 6 | 0xfff00000 - 0xffffffff |
| 7 | |
| 8 | The flash chip is really only 512Kbytes, but the high address bit of |
| 9 | the 1Meg region is ignored, so the flash is replicated through the |
| 10 | region. Thus, this is consistent with a flash base address 0xfff80000. |
| 11 | |
| 12 | The placement at the end is to be consistent with reset behavior, |
| 13 | where the processor itself initially uses this bus to load the branch |
| 14 | vector and start running. |
| 15 | |
| 16 | On-Chip Memory |
| 17 | -------------- |
| 18 | |
| 19 | 0xf4000000 - 0xf4000fff |
| 20 | |
| 21 | The 405GPr includes a 4K on-chip memory that can be placed however |
| 22 | software chooses. I choose to place the memory at this address, to |
| 23 | keep it out of the cachable areas. |
| 24 | |
| 25 | |
| 26 | Memory Bank 1 -- SystemACE Controller |
| 27 | ------------------------------------- |
| 28 | |
| 29 | 0xf0000000 - 0xf00fffff |
| 30 | |
| 31 | The SystemACE chip is along on peripheral bank CS#1. We don't need |
| 32 | much space, but 1Meg is the smallest we can configure the chip to |
| 33 | allocate. We need it far away from the flash region, because this |
| 34 | region is set to be non-cached. |
| 35 | |
| 36 | |
| 37 | Internal Peripherals |
| 38 | -------------------- |
| 39 | |
| 40 | 0xef600300 - 0xef6008ff |
| 41 | |
| 42 | These are scattered various peripherals internal to the PPC405GPr |
| 43 | chip. |
| 44 | |
| 45 | SDRAM |
| 46 | ----- |
| 47 | |
| 48 | 0x00000000 - 0x07ffffff (128 MBytes) |