Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Overview: |
| 3 | * Platform independend driver for NDFC (NanD Flash Controller) |
Stefan Roese | 982511e | 2009-05-20 10:58:01 +0200 | [diff] [blame] | 4 | * integrated into IBM/AMCC PPC4xx cores |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 5 | * |
Stefan Roese | 982511e | 2009-05-20 10:58:01 +0200 | [diff] [blame] | 6 | * (C) Copyright 2006-2009 |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 7 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 8 | * |
| 9 | * Based on original work by |
| 10 | * Thomas Gleixner |
| 11 | * Copyright 2006 IBM |
| 12 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 13 | * SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <common.h> |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 17 | #include <nand.h> |
| 18 | #include <linux/mtd/ndfc.h> |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 19 | #include <linux/mtd/nand_ecc.h> |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 20 | #include <asm/processor.h> |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 21 | #include <asm/io.h> |
Stefan Roese | 247e9d7 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 22 | #include <asm/ppc4xx.h> |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 23 | |
Alex Waterman | cd6aae3 | 2011-05-19 15:08:36 -0400 | [diff] [blame] | 24 | #ifndef CONFIG_SYS_NAND_BCR |
| 25 | #define CONFIG_SYS_NAND_BCR 0x80002222 |
| 26 | #endif |
| 27 | #ifndef CONFIG_SYS_NDFC_EBC0_CFG |
| 28 | #define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000 |
| 29 | #endif |
| 30 | |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 31 | /* |
| 32 | * We need to store the info, which chip-select (CS) is used for the |
| 33 | * chip number. For example on Sequoia NAND chip #0 uses |
| 34 | * CS #3. |
| 35 | */ |
| 36 | static int ndfc_cs[NDFC_MAX_BANKS]; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 37 | |
William Juul | 52c0796 | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 38 | static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 39 | { |
William Juul | 9e9c2c1 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 40 | struct nand_chip *this = mtd->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 41 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 42 | |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 43 | if (cmd == NAND_CMD_NONE) |
| 44 | return; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 45 | |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 46 | if (ctrl & NAND_CLE) |
| 47 | out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF); |
| 48 | else |
| 49 | out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 50 | } |
| 51 | |
| 52 | static int ndfc_dev_ready(struct mtd_info *mtdinfo) |
| 53 | { |
Wolfgang Denk | 4df0da5 | 2006-10-09 00:42:01 +0200 | [diff] [blame] | 54 | struct nand_chip *this = mtdinfo->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 55 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 56 | |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 57 | return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 58 | } |
| 59 | |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 60 | static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode) |
| 61 | { |
| 62 | struct nand_chip *this = mtdinfo->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 63 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 64 | u32 ccr; |
| 65 | |
| 66 | ccr = in_be32((u32 *)(base + NDFC_CCR)); |
| 67 | ccr |= NDFC_CCR_RESET_ECC; |
| 68 | out_be32((u32 *)(base + NDFC_CCR), ccr); |
| 69 | } |
| 70 | |
| 71 | static int ndfc_calculate_ecc(struct mtd_info *mtdinfo, |
| 72 | const u_char *dat, u_char *ecc_code) |
| 73 | { |
| 74 | struct nand_chip *this = mtdinfo->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 75 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 76 | u32 ecc; |
| 77 | u8 *p = (u8 *)&ecc; |
| 78 | |
| 79 | ecc = in_be32((u32 *)(base + NDFC_ECC)); |
| 80 | |
| 81 | /* The NDFC uses Smart Media (SMC) bytes order |
| 82 | */ |
Feng Kan | 50db6f2 | 2009-08-21 10:59:42 -0700 | [diff] [blame] | 83 | ecc_code[0] = p[1]; |
| 84 | ecc_code[1] = p[2]; |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 85 | ecc_code[2] = p[3]; |
| 86 | |
| 87 | return 0; |
| 88 | } |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 89 | |
| 90 | /* |
| 91 | * Speedups for buffer read/write/verify |
| 92 | * |
| 93 | * NDFC allows 32bit read/write of data. So we can speed up the buffer |
| 94 | * functions. No further checking, as nand_base will always read/write |
| 95 | * page aligned. |
| 96 | */ |
| 97 | static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) |
| 98 | { |
Wolfgang Denk | 4df0da5 | 2006-10-09 00:42:01 +0200 | [diff] [blame] | 99 | struct nand_chip *this = mtdinfo->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 100 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 101 | uint32_t *p = (uint32_t *) buf; |
| 102 | |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 103 | for (;len > 0; len -= 4) |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 104 | *p++ = in_be32((u32 *)(base + NDFC_DATA)); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 105 | } |
| 106 | |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 107 | #ifndef CONFIG_NAND_SPL |
| 108 | /* |
| 109 | * Don't use these speedup functions in NAND boot image, since the image |
| 110 | * has to fit into 4kByte. |
| 111 | */ |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 112 | static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) |
| 113 | { |
Wolfgang Denk | 4df0da5 | 2006-10-09 00:42:01 +0200 | [diff] [blame] | 114 | struct nand_chip *this = mtdinfo->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 115 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 116 | uint32_t *p = (uint32_t *) buf; |
| 117 | |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 118 | for (; len > 0; len -= 4) |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 119 | out_be32((u32 *)(base + NDFC_DATA), *p++); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) |
| 123 | { |
Wolfgang Denk | 4df0da5 | 2006-10-09 00:42:01 +0200 | [diff] [blame] | 124 | struct nand_chip *this = mtdinfo->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 125 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 126 | uint32_t *p = (uint32_t *) buf; |
| 127 | |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 128 | for (; len > 0; len -= 4) |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 129 | if (*p++ != in_be32((u32 *)(base + NDFC_DATA))) |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 130 | return -1; |
| 131 | |
| 132 | return 0; |
| 133 | } |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 134 | |
Alex Waterman | cd6aae3 | 2011-05-19 15:08:36 -0400 | [diff] [blame] | 135 | /* |
| 136 | * Read a byte from the NDFC. |
| 137 | */ |
| 138 | static uint8_t ndfc_read_byte(struct mtd_info *mtd) |
| 139 | { |
| 140 | |
| 141 | struct nand_chip *chip = mtd->priv; |
| 142 | |
Fabio Estevam | f17e878 | 2013-04-11 09:35:34 +0000 | [diff] [blame] | 143 | #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT |
Alex Waterman | cd6aae3 | 2011-05-19 15:08:36 -0400 | [diff] [blame] | 144 | return (uint8_t) readw(chip->IO_ADDR_R); |
| 145 | #else |
| 146 | return readb(chip->IO_ADDR_R); |
Wolfgang Ocker | aa36c3c | 2008-08-26 19:55:23 +0200 | [diff] [blame] | 147 | #endif |
| 148 | |
Alex Waterman | cd6aae3 | 2011-05-19 15:08:36 -0400 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | #endif /* #ifndef CONFIG_NAND_SPL */ |
| 152 | |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 153 | void board_nand_select_device(struct nand_chip *nand, int chip) |
| 154 | { |
Stefan Roese | d07e572 | 2006-10-24 18:06:48 +0200 | [diff] [blame] | 155 | /* |
| 156 | * Don't use "chip" to address the NAND device, |
| 157 | * generate the cs from the address where it is encoded. |
| 158 | */ |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 159 | ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00; |
| 160 | int cs = ndfc_cs[chip]; |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 161 | |
| 162 | /* Set NandFlash Core Configuration Register */ |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 163 | /* 1 col x 2 rows */ |
| 164 | out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24)); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 165 | out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR); |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 166 | } |
| 167 | |
Stefan Roese | 7b86c2b | 2008-08-29 11:56:49 +0200 | [diff] [blame] | 168 | static void ndfc_select_chip(struct mtd_info *mtd, int chip) |
| 169 | { |
| 170 | /* |
| 171 | * Nothing to do here! |
| 172 | */ |
| 173 | } |
| 174 | |
Heiko Schocher | 3ec4366 | 2006-12-21 17:17:02 +0100 | [diff] [blame] | 175 | int board_nand_init(struct nand_chip *nand) |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 176 | { |
Stefan Roese | d07e572 | 2006-10-24 18:06:48 +0200 | [diff] [blame] | 177 | int cs = (ulong)nand->IO_ADDR_W & 0x00000003; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 178 | ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00; |
| 179 | static int chip = 0; |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 180 | |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 181 | /* |
| 182 | * Save chip-select for this chip # |
| 183 | */ |
| 184 | ndfc_cs[chip] = cs; |
| 185 | |
| 186 | /* |
| 187 | * Select required NAND chip in NDFC |
| 188 | */ |
| 189 | board_nand_select_device(nand, chip); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 190 | |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 191 | nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA); |
| 192 | nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA); |
| 193 | nand->cmd_ctrl = ndfc_hwcontrol; |
| 194 | nand->chip_delay = 50; |
| 195 | nand->read_buf = ndfc_read_buf; |
| 196 | nand->dev_ready = ndfc_dev_ready; |
William Juul | 9e9c2c1 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 197 | nand->ecc.correct = nand_correct_data; |
| 198 | nand->ecc.hwctl = ndfc_enable_hwecc; |
| 199 | nand->ecc.calculate = ndfc_calculate_ecc; |
| 200 | nand->ecc.mode = NAND_ECC_HW; |
| 201 | nand->ecc.size = 256; |
| 202 | nand->ecc.bytes = 3; |
Sergey Lapin | 3a38a55 | 2013-01-14 03:46:50 +0000 | [diff] [blame] | 203 | nand->ecc.strength = 1; |
Stefan Roese | 7b86c2b | 2008-08-29 11:56:49 +0200 | [diff] [blame] | 204 | nand->select_chip = ndfc_select_chip; |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 205 | |
Fabio Estevam | f17e878 | 2013-04-11 09:35:34 +0000 | [diff] [blame] | 206 | #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT |
Alex Waterman | cd6aae3 | 2011-05-19 15:08:36 -0400 | [diff] [blame] | 207 | nand->options |= NAND_BUSWIDTH_16; |
| 208 | #endif |
| 209 | |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 210 | #ifndef CONFIG_NAND_SPL |
| 211 | nand->write_buf = ndfc_write_buf; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 212 | nand->verify_buf = ndfc_verify_buf; |
Alex Waterman | cd6aae3 | 2011-05-19 15:08:36 -0400 | [diff] [blame] | 213 | nand->read_byte = ndfc_read_byte; |
Stefan Roese | 585b5f54 | 2010-11-23 14:32:48 +0100 | [diff] [blame] | 214 | |
| 215 | chip++; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 216 | #else |
| 217 | /* |
| 218 | * Setup EBC (CS0 only right now) |
| 219 | */ |
Alex Waterman | cd6aae3 | 2011-05-19 15:08:36 -0400 | [diff] [blame] | 220 | mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 221 | |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 222 | mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); |
| 223 | mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 224 | #endif |
| 225 | |
Heiko Schocher | 3ec4366 | 2006-12-21 17:17:02 +0100 | [diff] [blame] | 226 | return 0; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 227 | } |