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Stefan Roese42fbddd2006-09-07 11:51:23 +02001/*
2 * Overview:
3 * Platform independend driver for NDFC (NanD Flash Controller)
Stefan Roese982511e2009-05-20 10:58:01 +02004 * integrated into IBM/AMCC PPC4xx cores
Stefan Roese42fbddd2006-09-07 11:51:23 +02005 *
Stefan Roese982511e2009-05-20 10:58:01 +02006 * (C) Copyright 2006-2009
Stefan Roese42fbddd2006-09-07 11:51:23 +02007 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * Based on original work by
10 * Thomas Gleixner
11 * Copyright 2006 IBM
12 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020013 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese42fbddd2006-09-07 11:51:23 +020014 */
15
16#include <common.h>
Stefan Roese42fbddd2006-09-07 11:51:23 +020017#include <nand.h>
18#include <linux/mtd/ndfc.h>
Stefan Roese1eb122a2007-06-01 15:15:12 +020019#include <linux/mtd/nand_ecc.h>
Stefan Roese42fbddd2006-09-07 11:51:23 +020020#include <asm/processor.h>
Stefan Roese1eb122a2007-06-01 15:15:12 +020021#include <asm/io.h>
Stefan Roese247e9d72010-09-09 19:18:00 +020022#include <asm/ppc4xx.h>
Stefan Roese42fbddd2006-09-07 11:51:23 +020023
Alex Watermancd6aae32011-05-19 15:08:36 -040024#ifndef CONFIG_SYS_NAND_BCR
25#define CONFIG_SYS_NAND_BCR 0x80002222
26#endif
27#ifndef CONFIG_SYS_NDFC_EBC0_CFG
28#define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000
29#endif
30
Stefan Roese0556a2a2008-01-05 16:47:58 +010031/*
32 * We need to store the info, which chip-select (CS) is used for the
33 * chip number. For example on Sequoia NAND chip #0 uses
34 * CS #3.
35 */
36static int ndfc_cs[NDFC_MAX_BANKS];
Stefan Roese42fbddd2006-09-07 11:51:23 +020037
William Juul52c07962007-10-31 13:53:06 +010038static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
Stefan Roese42fbddd2006-09-07 11:51:23 +020039{
William Juul9e9c2c12007-11-09 13:32:30 +010040 struct nand_chip *this = mtd->priv;
Stefan Roese0556a2a2008-01-05 16:47:58 +010041 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
Stefan Roese42fbddd2006-09-07 11:51:23 +020042
Stefan Roese0556a2a2008-01-05 16:47:58 +010043 if (cmd == NAND_CMD_NONE)
44 return;
Stefan Roese42fbddd2006-09-07 11:51:23 +020045
Stefan Roese0556a2a2008-01-05 16:47:58 +010046 if (ctrl & NAND_CLE)
47 out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF);
48 else
49 out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF);
Stefan Roese42fbddd2006-09-07 11:51:23 +020050}
51
52static int ndfc_dev_ready(struct mtd_info *mtdinfo)
53{
Wolfgang Denk4df0da52006-10-09 00:42:01 +020054 struct nand_chip *this = mtdinfo->priv;
Stefan Roese0556a2a2008-01-05 16:47:58 +010055 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
Stefan Roese42fbddd2006-09-07 11:51:23 +020056
Stefan Roese0556a2a2008-01-05 16:47:58 +010057 return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
Stefan Roese42fbddd2006-09-07 11:51:23 +020058}
59
Stefan Roese1eb122a2007-06-01 15:15:12 +020060static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
61{
62 struct nand_chip *this = mtdinfo->priv;
Stefan Roese0556a2a2008-01-05 16:47:58 +010063 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
Stefan Roese1eb122a2007-06-01 15:15:12 +020064 u32 ccr;
65
66 ccr = in_be32((u32 *)(base + NDFC_CCR));
67 ccr |= NDFC_CCR_RESET_ECC;
68 out_be32((u32 *)(base + NDFC_CCR), ccr);
69}
70
71static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
72 const u_char *dat, u_char *ecc_code)
73{
74 struct nand_chip *this = mtdinfo->priv;
Stefan Roese0556a2a2008-01-05 16:47:58 +010075 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
Stefan Roese1eb122a2007-06-01 15:15:12 +020076 u32 ecc;
77 u8 *p = (u8 *)&ecc;
78
79 ecc = in_be32((u32 *)(base + NDFC_ECC));
80
81 /* The NDFC uses Smart Media (SMC) bytes order
82 */
Feng Kan50db6f22009-08-21 10:59:42 -070083 ecc_code[0] = p[1];
84 ecc_code[1] = p[2];
Stefan Roese1eb122a2007-06-01 15:15:12 +020085 ecc_code[2] = p[3];
86
87 return 0;
88}
Stefan Roese42fbddd2006-09-07 11:51:23 +020089
90/*
91 * Speedups for buffer read/write/verify
92 *
93 * NDFC allows 32bit read/write of data. So we can speed up the buffer
94 * functions. No further checking, as nand_base will always read/write
95 * page aligned.
96 */
97static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
98{
Wolfgang Denk4df0da52006-10-09 00:42:01 +020099 struct nand_chip *this = mtdinfo->priv;
Stefan Roese0556a2a2008-01-05 16:47:58 +0100100 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
Stefan Roese42fbddd2006-09-07 11:51:23 +0200101 uint32_t *p = (uint32_t *) buf;
102
Stefan Roese3cdd3fd2006-10-20 14:28:52 +0200103 for (;len > 0; len -= 4)
Stefan Roese1eb122a2007-06-01 15:15:12 +0200104 *p++ = in_be32((u32 *)(base + NDFC_DATA));
Stefan Roese42fbddd2006-09-07 11:51:23 +0200105}
106
Stefan Roese1eb122a2007-06-01 15:15:12 +0200107#ifndef CONFIG_NAND_SPL
108/*
109 * Don't use these speedup functions in NAND boot image, since the image
110 * has to fit into 4kByte.
111 */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200112static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
113{
Wolfgang Denk4df0da52006-10-09 00:42:01 +0200114 struct nand_chip *this = mtdinfo->priv;
Stefan Roese0556a2a2008-01-05 16:47:58 +0100115 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
Stefan Roese42fbddd2006-09-07 11:51:23 +0200116 uint32_t *p = (uint32_t *) buf;
117
Stefan Roese3cdd3fd2006-10-20 14:28:52 +0200118 for (; len > 0; len -= 4)
Stefan Roese1eb122a2007-06-01 15:15:12 +0200119 out_be32((u32 *)(base + NDFC_DATA), *p++);
Stefan Roese42fbddd2006-09-07 11:51:23 +0200120}
121
122static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
123{
Wolfgang Denk4df0da52006-10-09 00:42:01 +0200124 struct nand_chip *this = mtdinfo->priv;
Stefan Roese0556a2a2008-01-05 16:47:58 +0100125 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
Stefan Roese42fbddd2006-09-07 11:51:23 +0200126 uint32_t *p = (uint32_t *) buf;
127
Stefan Roese3cdd3fd2006-10-20 14:28:52 +0200128 for (; len > 0; len -= 4)
Stefan Roese1eb122a2007-06-01 15:15:12 +0200129 if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
Stefan Roese42fbddd2006-09-07 11:51:23 +0200130 return -1;
131
132 return 0;
133}
Stefan Roese42fbddd2006-09-07 11:51:23 +0200134
Alex Watermancd6aae32011-05-19 15:08:36 -0400135/*
136 * Read a byte from the NDFC.
137 */
138static uint8_t ndfc_read_byte(struct mtd_info *mtd)
139{
140
141 struct nand_chip *chip = mtd->priv;
142
Fabio Estevamf17e8782013-04-11 09:35:34 +0000143#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
Alex Watermancd6aae32011-05-19 15:08:36 -0400144 return (uint8_t) readw(chip->IO_ADDR_R);
145#else
146 return readb(chip->IO_ADDR_R);
Wolfgang Ockeraa36c3c2008-08-26 19:55:23 +0200147#endif
148
Alex Watermancd6aae32011-05-19 15:08:36 -0400149}
150
151#endif /* #ifndef CONFIG_NAND_SPL */
152
Stefan Roese3cdd3fd2006-10-20 14:28:52 +0200153void board_nand_select_device(struct nand_chip *nand, int chip)
154{
Stefan Roesed07e5722006-10-24 18:06:48 +0200155 /*
156 * Don't use "chip" to address the NAND device,
157 * generate the cs from the address where it is encoded.
158 */
Stefan Roese0556a2a2008-01-05 16:47:58 +0100159 ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
160 int cs = ndfc_cs[chip];
Stefan Roese3cdd3fd2006-10-20 14:28:52 +0200161
162 /* Set NandFlash Core Configuration Register */
Stefan Roese1eb122a2007-06-01 15:15:12 +0200163 /* 1 col x 2 rows */
164 out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165 out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
Stefan Roese3cdd3fd2006-10-20 14:28:52 +0200166}
167
Stefan Roese7b86c2b2008-08-29 11:56:49 +0200168static void ndfc_select_chip(struct mtd_info *mtd, int chip)
169{
170 /*
171 * Nothing to do here!
172 */
173}
174
Heiko Schocher3ec43662006-12-21 17:17:02 +0100175int board_nand_init(struct nand_chip *nand)
Stefan Roese42fbddd2006-09-07 11:51:23 +0200176{
Stefan Roesed07e5722006-10-24 18:06:48 +0200177 int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
Stefan Roese0556a2a2008-01-05 16:47:58 +0100178 ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
179 static int chip = 0;
Stefan Roese3cdd3fd2006-10-20 14:28:52 +0200180
Stefan Roese0556a2a2008-01-05 16:47:58 +0100181 /*
182 * Save chip-select for this chip #
183 */
184 ndfc_cs[chip] = cs;
185
186 /*
187 * Select required NAND chip in NDFC
188 */
189 board_nand_select_device(nand, chip);
Stefan Roese42fbddd2006-09-07 11:51:23 +0200190
Stefan Roese0556a2a2008-01-05 16:47:58 +0100191 nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA);
192 nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA);
193 nand->cmd_ctrl = ndfc_hwcontrol;
194 nand->chip_delay = 50;
195 nand->read_buf = ndfc_read_buf;
196 nand->dev_ready = ndfc_dev_ready;
William Juul9e9c2c12007-11-09 13:32:30 +0100197 nand->ecc.correct = nand_correct_data;
198 nand->ecc.hwctl = ndfc_enable_hwecc;
199 nand->ecc.calculate = ndfc_calculate_ecc;
200 nand->ecc.mode = NAND_ECC_HW;
201 nand->ecc.size = 256;
202 nand->ecc.bytes = 3;
Sergey Lapin3a38a552013-01-14 03:46:50 +0000203 nand->ecc.strength = 1;
Stefan Roese7b86c2b2008-08-29 11:56:49 +0200204 nand->select_chip = ndfc_select_chip;
Stefan Roese1eb122a2007-06-01 15:15:12 +0200205
Fabio Estevamf17e8782013-04-11 09:35:34 +0000206#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
Alex Watermancd6aae32011-05-19 15:08:36 -0400207 nand->options |= NAND_BUSWIDTH_16;
208#endif
209
Stefan Roese42fbddd2006-09-07 11:51:23 +0200210#ifndef CONFIG_NAND_SPL
211 nand->write_buf = ndfc_write_buf;
Stefan Roese42fbddd2006-09-07 11:51:23 +0200212 nand->verify_buf = ndfc_verify_buf;
Alex Watermancd6aae32011-05-19 15:08:36 -0400213 nand->read_byte = ndfc_read_byte;
Stefan Roese585b5f542010-11-23 14:32:48 +0100214
215 chip++;
Stefan Roese42fbddd2006-09-07 11:51:23 +0200216#else
217 /*
218 * Setup EBC (CS0 only right now)
219 */
Alex Watermancd6aae32011-05-19 15:08:36 -0400220 mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG);
Stefan Roese42fbddd2006-09-07 11:51:23 +0200221
Stefan Roese918010a2009-09-09 16:25:29 +0200222 mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
223 mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
Stefan Roese42fbddd2006-09-07 11:51:23 +0200224#endif
225
Heiko Schocher3ec43662006-12-21 17:17:02 +0100226 return 0;
Stefan Roese42fbddd2006-09-07 11:51:23 +0200227}