blob: ce23427b1744e3261a8f56549090f66324932c18 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roese5a44c602007-10-21 08:16:12 +02002/*
3 * (C) Copyright 2007
4 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 *
6 * based on a the Linux rtc-x1207.c driver which is:
7 * Copyright 2004 Karen Spearel
8 * Copyright 2005 Alessandro Zummo
9 *
10 * Information and datasheet:
11 * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
Stefan Roese5a44c602007-10-21 08:16:12 +020012 */
13
14/*
15 * Date & Time support for Xicor/Intersil X1205 RTC
16 */
17
18/* #define DEBUG */
19
20#include <common.h>
21#include <command.h>
Simon Glass0f2af882020-05-10 11:40:05 -060022#include <log.h>
Stefan Roese5a44c602007-10-21 08:16:12 +020023#include <rtc.h>
24#include <i2c.h>
Stefan Roese5a44c602007-10-21 08:16:12 +020025
Stefan Roese5a44c602007-10-21 08:16:12 +020026#define CCR_SEC 0
27#define CCR_MIN 1
28#define CCR_HOUR 2
29#define CCR_MDAY 3
30#define CCR_MONTH 4
31#define CCR_YEAR 5
32#define CCR_WDAY 6
33#define CCR_Y2K 7
34
35#define X1205_REG_SR 0x3F /* status register */
36#define X1205_REG_Y2K 0x37
37#define X1205_REG_DW 0x36
38#define X1205_REG_YR 0x35
39#define X1205_REG_MO 0x34
40#define X1205_REG_DT 0x33
41#define X1205_REG_HR 0x32
42#define X1205_REG_MN 0x31
43#define X1205_REG_SC 0x30
44#define X1205_REG_DTR 0x13
45#define X1205_REG_ATR 0x12
46#define X1205_REG_INT 0x11
47#define X1205_REG_0 0x10
48#define X1205_REG_Y2K1 0x0F
49#define X1205_REG_DWA1 0x0E
50#define X1205_REG_YRA1 0x0D
51#define X1205_REG_MOA1 0x0C
52#define X1205_REG_DTA1 0x0B
53#define X1205_REG_HRA1 0x0A
54#define X1205_REG_MNA1 0x09
55#define X1205_REG_SCA1 0x08
56#define X1205_REG_Y2K0 0x07
57#define X1205_REG_DWA0 0x06
58#define X1205_REG_YRA0 0x05
59#define X1205_REG_MOA0 0x04
60#define X1205_REG_DTA0 0x03
61#define X1205_REG_HRA0 0x02
62#define X1205_REG_MNA0 0x01
63#define X1205_REG_SCA0 0x00
64
65#define X1205_CCR_BASE 0x30 /* Base address of CCR */
66#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
67
68#define X1205_SR_RTCF 0x01 /* Clock failure */
69#define X1205_SR_WEL 0x02 /* Write Enable Latch */
70#define X1205_SR_RWEL 0x04 /* Register Write Enable */
71
72#define X1205_DTR_DTR0 0x01
73#define X1205_DTR_DTR1 0x02
74#define X1205_DTR_DTR2 0x04
75
76#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
77
78static void rtc_write(int reg, u8 val)
79{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
Stefan Roese5a44c602007-10-21 08:16:12 +020081}
82
83/*
84 * In the routines that deal directly with the x1205 hardware, we use
85 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
86 * Epoch is initialized as 2000. Time is set to UTC.
87 */
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030088int rtc_get(struct rtc_time *tm)
Stefan Roese5a44c602007-10-21 08:16:12 +020089{
90 u8 buf[8];
91
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
Stefan Roese5a44c602007-10-21 08:16:12 +020093
94 debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
95 "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
96 __FUNCTION__,
97 buf[0], buf[1], buf[2], buf[3],
98 buf[4], buf[5], buf[6], buf[7]);
99
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200100 tm->tm_sec = bcd2bin(buf[CCR_SEC]);
101 tm->tm_min = bcd2bin(buf[CCR_MIN]);
102 tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
103 tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
104 tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */
105 tm->tm_year = bcd2bin(buf[CCR_YEAR])
106 + (bcd2bin(buf[CCR_Y2K]) * 100);
Stefan Roese5a44c602007-10-21 08:16:12 +0200107 tm->tm_wday = buf[CCR_WDAY];
108
109 debug("%s: tm is secs=%d, mins=%d, hours=%d, "
110 "mday=%d, mon=%d, year=%d, wday=%d\n",
111 __FUNCTION__,
112 tm->tm_sec, tm->tm_min, tm->tm_hour,
113 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300114
115 return 0;
Stefan Roese5a44c602007-10-21 08:16:12 +0200116}
117
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200118int rtc_set(struct rtc_time *tm)
Stefan Roese5a44c602007-10-21 08:16:12 +0200119{
120 int i;
121 u8 buf[8];
122
123 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
124 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
125 tm->tm_hour, tm->tm_min, tm->tm_sec);
126
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200127 buf[CCR_SEC] = bin2bcd(tm->tm_sec);
128 buf[CCR_MIN] = bin2bcd(tm->tm_min);
Stefan Roese5a44c602007-10-21 08:16:12 +0200129
130 /* set hour and 24hr bit */
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200131 buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;
Stefan Roese5a44c602007-10-21 08:16:12 +0200132
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200133 buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
Stefan Roese5a44c602007-10-21 08:16:12 +0200134
135 /* month, 1 - 12 */
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200136 buf[CCR_MONTH] = bin2bcd(tm->tm_mon);
Stefan Roese5a44c602007-10-21 08:16:12 +0200137
138 /* year, since the rtc epoch*/
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200139 buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
Stefan Roese5a44c602007-10-21 08:16:12 +0200140 buf[CCR_WDAY] = tm->tm_wday & 0x07;
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200141 buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100);
Stefan Roese5a44c602007-10-21 08:16:12 +0200142
143 /* this sequence is required to unlock the chip */
144 rtc_write(X1205_REG_SR, X1205_SR_WEL);
145 rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL);
146
147 /* write register's data */
148 for (i = 0; i < 8; i++)
149 rtc_write(X1205_CCR_BASE + i, buf[i]);
150
151 rtc_write(X1205_REG_SR, 0);
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200152
153 return 0;
Stefan Roese5a44c602007-10-21 08:16:12 +0200154}
155
156void rtc_reset(void)
157{
158 /*
159 * Nothing to do
160 */
161}