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git01.mediatek.com / filogic / uboot / 6408566c95f5221ae65794bd4740d04902835c06 / . / dts / upstream / src / powerpc / pdm360ng.dts
blob: 67c3b9db75d76a3b0f87c97241804c3a72d317af [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Device Tree Source for IFM PDM360NG.
4 *
5 * Copyright 2009 - 2010 DENX Software Engineering.
6 * Anatolij Gustschin <agust@denx.de>
7 *
8 * Based on MPC5121E ADS dts.
9 * Copyright 2008 Freescale Semiconductor Inc.
10 */
11
12#include "mpc5121.dtsi"
13
14/ {
15 model = "pdm360ng";
16 compatible = "ifm,pdm360ng", "fsl,mpc5121";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&ipic>;
20
21 memory {
22 device_type = "memory";
23 reg = <0x00000000 0x20000000>; // 512MB at 0
24 };
25
26 nfc@40000000 {
27 bank-width = <0x1>;
28 chips = <0x1>;
29
30 partition@0 {
31 label = "nand0";
32 reg = <0x0 0x40000000>;
33 };
34 };
35
36 localbus@80000020 {
37 ranges = <0x0 0x0 0xf0000000 0x10000000 /* Flash */
38 0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */
39
40 flash@0,0 {
41 compatible = "amd,s29gl01gp", "cfi-flash";
42 reg = <0 0x00000000 0x08000000
43 0 0x08000000 0x08000000>;
44 #address-cells = <1>;
45 #size-cells = <1>;
46 bank-width = <4>;
47 device-width = <2>;
48
49 partition@0 {
50 label = "u-boot";
51 reg = <0x00000000 0x00080000>;
52 read-only;
53 };
54 partition@80000 {
55 label = "environment";
56 reg = <0x00080000 0x00080000>;
57 read-only;
58 };
59 partition@100000 {
60 label = "splash-image";
61 reg = <0x00100000 0x00080000>;
62 read-only;
63 };
64 partition@180000 {
65 label = "device-tree";
66 reg = <0x00180000 0x00040000>;
67 };
68 partition@1c0000 {
69 label = "kernel";
70 reg = <0x001c0000 0x00500000>;
71 };
72 partition@6c0000 {
73 label = "filesystem";
74 reg = <0x006c0000 0x07940000>;
75 };
76 };
77
78 mram0@2,0 {
79 compatible = "mtd-ram";
80 reg = <2 0x00000 0x10000>;
81 bank-width = <2>;
82 };
83
84 mram1@2,10000 {
85 compatible = "mtd-ram";
86 reg = <2 0x010000 0x10000>;
87 bank-width = <2>;
88 };
89 };
90
91 soc@80000000 {
92
93 i2c@1700 {
94 fsl,preserve-clocking;
95
96 eeprom@50 {
97 compatible = "atmel,24c01";
98 reg = <0x50>;
99 };
100
101 rtc@68 {
102 compatible = "st,m41t00";
103 reg = <0x68>;
104 };
105 };
106
107 i2c@1720 {
108 status = "disabled";
109 };
110
111 i2c@1740 {
112 fsl,preserve-clocking;
113 };
114
115 ethernet@2800 {
116 phy-handle = <&phy0>;
117 };
118
119 mdio@2800 {
120 phy0: ethernet-phy@1f {
121 compatible = "smsc,lan8700";
122 reg = <0x1f>;
123 };
124 };
125
126 /* USB1 using external ULPI PHY */
127 usb@3000 {
128 dr_mode = "host";
129 };
130
131 /* USB0 using internal UTMI PHY */
132 usb@4000 {
133 fsl,invert-pwr-fault;
134 };
135
136 psc@11000 {
137 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
138 };
139
140 psc@11100 {
141 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
142 };
143
144 psc@11200 {
145 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
146 };
147
148 psc@11300 {
149 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
150 };
151
152 psc@11400 {
153 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
154 };
155
156 psc@11500 {
157 status = "disabled";
158 };
159
160 psc@11600 {
161 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
162 };
163
164 psc@11700 {
165 status = "disabled";
166 };
167
168 psc@11800 {
169 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
170 };
171
172 psc@11900 {
173 compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
174 #address-cells = <1>;
175 #size-cells = <0>;
176
177 /* ADS7845 touch screen controller */
178 ts@0 {
179 compatible = "ti,ads7846";
180 reg = <0x0>;
181 spi-max-frequency = <3000000>;
182 /* pen irq is GPIO25 */
183 interrupts = <78 0x8>;
184 };
185 };
186
187 psc@11a00 {
188 status = "disabled";
189 };
190
191 psc@11b00 {
192 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
193 };
194 };
195};