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git01.mediatek.com / filogic / uboot / 6408566c95f5221ae65794bd4740d04902835c06 / . / dts / upstream / src / powerpc / mpc5200b.dtsi
blob: ffa82c7e1055692b67579a1686601790c45551e0 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * base MPC5200b Device Tree Source
4 *
5 * Copyright (C) 2010 SecretLab
6 * Grant Likely <grant@secretlab.ca>
7 * John Bonesio <bones@secretlab.ca>
8 */
9
10/dts-v1/;
11
12/ {
13 model = "fsl,mpc5200b";
14 compatible = "fsl,mpc5200b";
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&mpc5200_pic>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 powerpc: PowerPC,5200@0 {
24 device_type = "cpu";
25 reg = <0>;
26 d-cache-line-size = <32>;
27 i-cache-line-size = <32>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
33 };
34 };
35
36 memory: memory@0 {
37 device_type = "memory";
38 reg = <0x00000000 0x04000000>; // 64MB
39 };
40
41 soc: soc5200@f0000000 {
42 #address-cells = <1>;
43 #size-cells = <1>;
44 compatible = "fsl,mpc5200b-immr";
45 ranges = <0 0xf0000000 0x0000c000>;
46 reg = <0xf0000000 0x00000100>;
47 bus-frequency = <0>; // from bootloader
48 system-frequency = <0>; // from bootloader
49
50 cdm@200 {
51 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
52 reg = <0x200 0x38>;
53 };
54
55 mpc5200_pic: interrupt-controller@500 {
56 // 5200 interrupts are encoded into two levels;
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
60 reg = <0x500 0x80>;
61 };
62
63 gpt0: timer@600 { // General Purpose Timer
64 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
65 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
66 reg = <0x600 0x10>;
67 interrupts = <1 9 0>;
68 // add 'fsl,has-wdt' to enable watchdog
69 };
70
71 gpt1: timer@610 { // General Purpose Timer
72 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
73 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
74 reg = <0x610 0x10>;
75 interrupts = <1 10 0>;
76 };
77
78 gpt2: timer@620 { // General Purpose Timer
79 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
80 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
81 reg = <0x620 0x10>;
82 interrupts = <1 11 0>;
83 };
84
85 gpt3: timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
88 reg = <0x630 0x10>;
89 interrupts = <1 12 0>;
90 };
91
92 gpt4: timer@640 { // General Purpose Timer
93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
94 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
95 reg = <0x640 0x10>;
96 interrupts = <1 13 0>;
97 };
98
99 gpt5: timer@650 { // General Purpose Timer
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
102 reg = <0x650 0x10>;
103 interrupts = <1 14 0>;
104 };
105
106 gpt6: timer@660 { // General Purpose Timer
107 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
108 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
109 reg = <0x660 0x10>;
110 interrupts = <1 15 0>;
111 };
112
113 gpt7: timer@670 { // General Purpose Timer
114 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
115 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
116 reg = <0x670 0x10>;
117 interrupts = <1 16 0>;
118 };
119
120 rtc@800 { // Real time clock
121 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
122 reg = <0x800 0x100>;
123 interrupts = <1 5 0 1 6 0>;
124 };
125
126 can@900 {
127 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
128 interrupts = <2 17 0>;
129 reg = <0x900 0x80>;
130 };
131
132 can@980 {
133 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
134 interrupts = <2 18 0>;
135 reg = <0x980 0x80>;
136 };
137
138 gpio_simple: gpio@b00 {
139 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
140 reg = <0xb00 0x40>;
141 interrupts = <1 7 0>;
142 gpio-controller;
143 #gpio-cells = <2>;
144 };
145
146 gpio_wkup: gpio@c00 {
147 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
148 reg = <0xc00 0x40>;
149 interrupts = <1 8 0 0 3 0>;
150 gpio-controller;
151 #gpio-cells = <2>;
152 };
153
154 spi@f00 {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
158 reg = <0xf00 0x20>;
159 interrupts = <2 13 0 2 14 0>;
160 };
161
162 usb: usb@1000 {
163 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
164 reg = <0x1000 0xff>;
165 interrupts = <2 6 0>;
166 };
167
168 dma-controller@1200 {
169 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
170 reg = <0x1200 0x80>;
171 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
172 3 4 0 3 5 0 3 6 0 3 7 0
173 3 8 0 3 9 0 3 10 0 3 11 0
174 3 12 0 3 13 0 3 14 0 3 15 0>;
175 };
176
177 xlb@1f00 {
178 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
179 reg = <0x1f00 0x100>;
180 };
181
182 psc1: psc@2000 { // PSC1
183 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
184 reg = <0x2000 0x100>;
185 interrupts = <2 1 0>;
186 };
187
188 psc2: psc@2200 { // PSC2
189 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
190 reg = <0x2200 0x100>;
191 interrupts = <2 2 0>;
192 };
193
194 psc3: psc@2400 { // PSC3
195 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
196 reg = <0x2400 0x100>;
197 interrupts = <2 3 0>;
198 };
199
200 psc4: psc@2600 { // PSC4
201 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
202 reg = <0x2600 0x100>;
203 interrupts = <2 11 0>;
204 };
205
206 psc5: psc@2800 { // PSC5
207 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
208 reg = <0x2800 0x100>;
209 interrupts = <2 12 0>;
210 };
211
212 psc6: psc@2c00 { // PSC6
213 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
214 reg = <0x2c00 0x100>;
215 interrupts = <2 4 0>;
216 };
217
218 eth0: ethernet@3000 {
219 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
220 reg = <0x3000 0x400>;
221 local-mac-address = [ 00 00 00 00 00 00 ];
222 interrupts = <2 5 0>;
223 };
224
225 mdio@3000 {
226 #address-cells = <1>;
227 #size-cells = <0>;
228 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
229 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
230 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
231 };
232
233 ata@3a00 {
234 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
235 reg = <0x3a00 0x100>;
236 interrupts = <2 7 0>;
237 };
238
239 sclpc@3c00 {
240 compatible = "fsl,mpc5200-lpbfifo";
241 reg = <0x3c00 0x60>;
242 interrupts = <2 23 0>;
243 };
244
245 i2c@3d00 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
249 reg = <0x3d00 0x40>;
250 interrupts = <2 15 0>;
251 };
252
253 i2c@3d40 {
254 #address-cells = <1>;
255 #size-cells = <0>;
256 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
257 reg = <0x3d40 0x40>;
258 interrupts = <2 16 0>;
259 };
260
261 sram@8000 {
262 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
263 reg = <0x8000 0x4000>;
264 };
265 };
266
267 pci: pci@f0000d00 {
268 #interrupt-cells = <1>;
269 #size-cells = <2>;
270 #address-cells = <3>;
271 device_type = "pci";
272 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
273 reg = <0xf0000d00 0x100>;
274 // interrupt-map-mask = need to add
275 // interrupt-map = need to add
276 clock-frequency = <0>; // From boot loader
277 interrupts = <2 8 0 2 9 0 2 10 0>;
278 bus-range = <0 0>;
279 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000>,
280 <0x02000000 0 0x90000000 0x90000000 0 0x10000000>,
281 <0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
282 };
283
284 localbus: localbus {
285 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
286 #address-cells = <2>;
287 #size-cells = <1>;
288 ranges = <0 0 0xfc000000 0x2000000>;
289 };
290};