| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Tegra on chip generic hardware timestamping engine (HTE) provider |
| 8 | |
| 9 | maintainers: |
| 10 | - Dipen Patel <dipenp@nvidia.com> |
| 11 | |
| 12 | description: |
| 13 | Tegra SoC has two instances of generic hardware timestamping engines (GTE) |
| 14 | known as GTE GPIO and GTE IRQ, which can monitor subset of GPIO and on chip |
| 15 | IRQ lines for the state change respectively, upon detection it will record |
| 16 | timestamp (taken from system counter) in its internal hardware FIFO. It has |
| 17 | a bitmap array arranged in 32bit slices where each bit represent signal/line |
| 18 | to enable or disable for the hardware timestamping. The GTE GPIO monitors |
| 19 | GPIO lines from the AON (always on) GPIO controller. |
| 20 | |
| 21 | properties: |
| 22 | compatible: |
| 23 | enum: |
| 24 | - nvidia,tegra194-gte-aon |
| 25 | - nvidia,tegra194-gte-lic |
| 26 | - nvidia,tegra234-gte-aon |
| 27 | - nvidia,tegra234-gte-lic |
| 28 | |
| 29 | reg: |
| 30 | maxItems: 1 |
| 31 | |
| 32 | interrupts: |
| 33 | maxItems: 1 |
| 34 | |
| 35 | nvidia,int-threshold: |
| 36 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 37 | description: |
| 38 | HTE device generates its interrupt based on this u32 FIFO threshold |
| 39 | value. The recommended value is 1. |
| 40 | minimum: 1 |
| 41 | maximum: 256 |
| 42 | |
| 43 | nvidia,slices: |
| 44 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 45 | deprecated: true |
| 46 | description: |
| 47 | HTE lines are arranged in 32 bit slice where each bit represents different |
| 48 | line/signal that it can enable/configure for the timestamp. It is u32 |
| 49 | property and the value depends on the HTE instance in the chip. The AON |
| 50 | GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194 |
| 51 | LIC instance has 11 slices and Tegra234 LIC has 17 slices. |
| 52 | enum: [3, 11, 17] |
| 53 | |
| 54 | nvidia,gpio-controller: |
| 55 | $ref: /schemas/types.yaml#/definitions/phandle |
| 56 | description: |
| 57 | The phandle to AON gpio controller instance. This is required to handle |
| 58 | namespace conversion between GPIO and GTE. |
| 59 | |
| 60 | '#timestamp-cells': |
| 61 | description: |
| 62 | This represents number of line id arguments as specified by the |
| 63 | consumers. For the GTE IRQ, this is IRQ number as mentioned in the |
| 64 | SoC technical reference manual. For the GTE GPIO, its value is same as |
| 65 | mentioned in the nvidia GPIO device tree binding document. |
| 66 | const: 1 |
| 67 | |
| 68 | required: |
| 69 | - compatible |
| 70 | - reg |
| 71 | - interrupts |
| 72 | - "#timestamp-cells" |
| 73 | |
| 74 | allOf: |
| 75 | - if: |
| 76 | properties: |
| 77 | compatible: |
| 78 | contains: |
| 79 | enum: |
| 80 | - nvidia,tegra194-gte-aon |
| 81 | - nvidia,tegra234-gte-aon |
| 82 | then: |
| 83 | properties: |
| 84 | nvidia,slices: |
| 85 | const: 3 |
| 86 | |
| 87 | - if: |
| 88 | properties: |
| 89 | compatible: |
| 90 | contains: |
| 91 | enum: |
| 92 | - nvidia,tegra194-gte-lic |
| 93 | then: |
| 94 | properties: |
| 95 | nvidia,slices: |
| 96 | const: 11 |
| 97 | |
| 98 | - if: |
| 99 | properties: |
| 100 | compatible: |
| 101 | contains: |
| 102 | enum: |
| 103 | - nvidia,tegra234-gte-lic |
| 104 | then: |
| 105 | properties: |
| 106 | nvidia,slices: |
| 107 | const: 17 |
| 108 | |
| 109 | - if: |
| 110 | properties: |
| 111 | compatible: |
| 112 | contains: |
| 113 | enum: |
| 114 | - nvidia,tegra234-gte-aon |
| 115 | then: |
| 116 | required: |
| 117 | - nvidia,gpio-controller |
| 118 | |
| 119 | additionalProperties: false |
| 120 | |
| 121 | examples: |
| 122 | - | |
| 123 | tegra_hte_aon: timestamp@c1e0000 { |
| 124 | compatible = "nvidia,tegra194-gte-aon"; |
| 125 | reg = <0xc1e0000 0x10000>; |
| 126 | interrupts = <0 13 0x4>; |
| 127 | nvidia,int-threshold = <1>; |
| 128 | #timestamp-cells = <1>; |
| 129 | }; |
| 130 | |
| 131 | - | |
| 132 | tegra_hte_lic: timestamp@3aa0000 { |
| 133 | compatible = "nvidia,tegra194-gte-lic"; |
| 134 | reg = <0x3aa0000 0x10000>; |
| 135 | interrupts = <0 11 0x4>; |
| 136 | nvidia,int-threshold = <1>; |
| 137 | #timestamp-cells = <1>; |
| 138 | }; |
| 139 | |
| 140 | ... |