| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Allwinner A31 Peripheral Reset Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Chen-Yu Tsai <wens@csie.org> |
| 11 | - Maxime Ripard <mripard@kernel.org> |
| 12 | |
| 13 | deprecated: true |
| 14 | |
| 15 | select: |
| 16 | properties: |
| 17 | compatible: |
| 18 | contains: |
| 19 | enum: |
| 20 | - allwinner,sun6i-a31-ahb1-reset |
| 21 | - allwinner,sun6i-a31-clock-reset |
| 22 | |
| 23 | # The PRCM on the A31 and A23 will have the reg property missing, |
| 24 | # since it's set at the upper level node, and will be validated by |
| 25 | # PRCM's schema. Make sure we only validate standalone nodes. |
| 26 | required: |
| 27 | - compatible |
| 28 | - reg |
| 29 | |
| 30 | properties: |
| 31 | "#reset-cells": |
| 32 | const: 1 |
| 33 | description: > |
| 34 | This additional argument passed to that reset controller is the |
| 35 | offset of the bit controlling this particular reset line in the |
| 36 | register. |
| 37 | |
| 38 | compatible: |
| 39 | enum: |
| 40 | - allwinner,sun6i-a31-ahb1-reset |
| 41 | - allwinner,sun6i-a31-clock-reset |
| 42 | |
| 43 | reg: |
| 44 | maxItems: 1 |
| 45 | |
| 46 | required: |
| 47 | - "#reset-cells" |
| 48 | - compatible |
| 49 | - reg |
| 50 | |
| 51 | additionalProperties: false |
| 52 | |
| 53 | examples: |
| 54 | - | |
| 55 | ahb1_rst: reset@1c202c0 { |
| 56 | #reset-cells = <1>; |
| 57 | compatible = "allwinner,sun6i-a31-ahb1-reset"; |
| 58 | reg = <0x01c202c0 0xc>; |
| 59 | }; |
| 60 | |
| 61 | - | |
| 62 | apbs_rst: reset@80014b0 { |
| 63 | #reset-cells = <1>; |
| 64 | compatible = "allwinner,sun6i-a31-clock-reset"; |
| 65 | reg = <0x080014b0 0x4>; |
| 66 | }; |
| 67 | |
| 68 | ... |