| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Renesas RZ/G2L Port Output Enable for GPT (POEG) |
| 8 | |
| 9 | maintainers: |
| 10 | - Biju Das <biju.das.jz@bp.renesas.com> |
| 11 | |
| 12 | description: | |
| 13 | The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT) can be |
| 14 | disabled by using the port output enabling function for the GPT (POEG). |
| 15 | Specifically, either of the following ways can be used. |
| 16 | * Input level detection of the GTETRGA to GTETRGD pins. |
| 17 | * Output-disable request from the GPT. |
| 18 | * SSF bit setting(ie, by setting POEGGn.SSF to 1) |
| 19 | |
| 20 | The state of the GTIOCxA and the GTIOCxB pins when the output is disabled, |
| 21 | are controlled by the GPT module. |
| 22 | |
| 23 | properties: |
| 24 | compatible: |
| 25 | items: |
| 26 | - enum: |
| 27 | - renesas,r9a07g044-poeg # RZ/G2{L,LC} |
| 28 | - renesas,r9a07g054-poeg # RZ/V2L |
| 29 | - const: renesas,rzg2l-poeg |
| 30 | |
| 31 | reg: |
| 32 | maxItems: 1 |
| 33 | |
| 34 | interrupts: |
| 35 | maxItems: 1 |
| 36 | |
| 37 | clocks: |
| 38 | maxItems: 1 |
| 39 | |
| 40 | power-domains: |
| 41 | maxItems: 1 |
| 42 | |
| 43 | resets: |
| 44 | maxItems: 1 |
| 45 | |
| 46 | renesas,gpt: |
| 47 | $ref: /schemas/types.yaml#/definitions/phandle |
| 48 | description: phandle to gpt instance that serves the pwm operation. |
| 49 | |
| 50 | renesas,poeg-id: |
| 51 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 52 | enum: [ 0, 1, 2, 3 ] |
| 53 | description: | |
| 54 | POEG group index. Valid values are: |
| 55 | <0> : POEG group A |
| 56 | <1> : POEG group B |
| 57 | <2> : POEG group C |
| 58 | <3> : POEG group D |
| 59 | |
| 60 | required: |
| 61 | - compatible |
| 62 | - reg |
| 63 | - interrupts |
| 64 | - clocks |
| 65 | - power-domains |
| 66 | - resets |
| 67 | - renesas,poeg-id |
| 68 | - renesas,gpt |
| 69 | |
| 70 | additionalProperties: false |
| 71 | |
| 72 | examples: |
| 73 | - | |
| 74 | #include <dt-bindings/clock/r9a07g044-cpg.h> |
| 75 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 76 | |
| 77 | poeggd: poeg@10049400 { |
| 78 | compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg"; |
| 79 | reg = <0x10049400 0x400>; |
| 80 | interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; |
| 81 | clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>; |
| 82 | power-domains = <&cpg>; |
| 83 | resets = <&cpg R9A07G044_POEG_D_RST>; |
| 84 | renesas,poeg-id = <3>; |
| 85 | renesas,gpt = <&gpt>; |
| 86 | }; |