| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pinctrl/qcom,sm4450-tlmm.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Qualcomm Technologies, Inc. SM4450 TLMM block |
| 8 | |
| 9 | maintainers: |
| 10 | - Tengfei Fan <quic_tengfan@quicinc.com> |
| 11 | |
| 12 | description: |
| 13 | Top Level Mode Multiplexer pin controller in Qualcomm SM4450 SoC. |
| 14 | |
| 15 | allOf: |
| 16 | - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# |
| 17 | |
| 18 | properties: |
| 19 | compatible: |
| Tom Rini | 6bb92fc | 2024-05-20 09:54:58 -0600 | [diff] [blame] | 20 | const: qcom,sm4450-tlmm |
| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 21 | |
| 22 | reg: |
| 23 | maxItems: 1 |
| 24 | |
| 25 | interrupts: true |
| 26 | interrupt-controller: true |
| 27 | "#interrupt-cells": true |
| 28 | gpio-controller: true |
| 29 | |
| 30 | gpio-reserved-ranges: |
| 31 | minItems: 1 |
| 32 | maxItems: 68 |
| 33 | |
| 34 | gpio-line-names: |
| 35 | maxItems: 136 |
| 36 | |
| 37 | "#gpio-cells": true |
| 38 | gpio-ranges: true |
| 39 | wakeup-parent: true |
| 40 | |
| 41 | patternProperties: |
| 42 | "-state$": |
| 43 | oneOf: |
| 44 | - $ref: "#/$defs/qcom-sm4450-tlmm-state" |
| 45 | - patternProperties: |
| 46 | "-pins$": |
| 47 | $ref: "#/$defs/qcom-sm4450-tlmm-state" |
| 48 | additionalProperties: false |
| 49 | |
| 50 | $defs: |
| 51 | qcom-sm4450-tlmm-state: |
| 52 | type: object |
| 53 | description: |
| 54 | Pinctrl node's client devices use subnodes for desired pin configuration. |
| 55 | Client device subnodes use below standard properties. |
| 56 | $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state |
| 57 | unevaluatedProperties: false |
| 58 | |
| 59 | properties: |
| 60 | pins: |
| 61 | description: |
| 62 | List of gpio pins affected by the properties specified in this |
| 63 | subnode. |
| 64 | items: |
| 65 | oneOf: |
| 66 | - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-5])$" |
| 67 | - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] |
| 68 | minItems: 1 |
| 69 | maxItems: 36 |
| 70 | |
| 71 | function: |
| 72 | description: |
| 73 | Specify the alternative function to be configured for the specified |
| 74 | pins. |
| 75 | enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2, |
| 76 | atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_usb02, |
| 77 | atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c, |
| 78 | cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, |
| 79 | cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, cri_trng, |
| 80 | cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, |
| 81 | dp0_hot, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, ibi_i3c, |
| 82 | jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, |
| 83 | mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, |
| 84 | mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, |
| 85 | mi2s_mclk1, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk, |
| 86 | phase_flag0, phase_flag1, phase_flag10, phase_flag11, |
| 87 | phase_flag12, phase_flag13, phase_flag14, phase_flag15, |
| 88 | phase_flag16, phase_flag17, phase_flag18, phase_flag19, |
| 89 | phase_flag2, phase_flag20, phase_flag21, phase_flag22, |
| 90 | phase_flag23, phase_flag24, phase_flag25, phase_flag26, |
| 91 | phase_flag27, phase_flag28, phase_flag29, phase_flag3, |
| 92 | phase_flag30, phase_flag31, phase_flag4, phase_flag5, |
| 93 | phase_flag6, phase_flag7, phase_flag8, phase_flag9, |
| 94 | pll_bist, pll_clk, prng_rosc0, prng_rosc1, prng_rosc2, |
| 95 | prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1, |
| 96 | qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, |
| 97 | qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, |
| 98 | qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable, |
| 99 | qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request, |
| 100 | qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, |
| 101 | qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5, |
| 102 | qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3, |
| 103 | qup1_se4, qup1_se5, qup1_se6, sd_write, tb_trig, tgu_ch0, |
| 104 | tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1, |
| 105 | tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, |
| 106 | uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, |
| 107 | uim1_present, uim1_reset, usb0_hs, usb0_phy, vfr_0, vfr_1, |
| 108 | vsense_trigger ] |
| 109 | |
| 110 | required: |
| 111 | - pins |
| 112 | |
| 113 | required: |
| 114 | - compatible |
| 115 | - reg |
| 116 | |
| 117 | additionalProperties: false |
| 118 | |
| 119 | examples: |
| 120 | - | |
| 121 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 122 | tlmm: pinctrl@f100000 { |
| 123 | compatible = "qcom,sm4450-tlmm"; |
| 124 | reg = <0x0f100000 0x300000>; |
| 125 | gpio-controller; |
| 126 | #gpio-cells = <2>; |
| 127 | gpio-ranges = <&tlmm 0 0 137>; |
| 128 | interrupt-controller; |
| 129 | #interrupt-cells = <2>; |
| 130 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| 131 | |
| 132 | gpio-wo-state { |
| 133 | pins = "gpio1"; |
| 134 | function = "gpio"; |
| 135 | }; |
| 136 | |
| 137 | uart-w-state { |
| 138 | rx-pins { |
| 139 | pins = "gpio23"; |
| 140 | function = "qup1_se2"; |
| 141 | bias-pull-up; |
| 142 | }; |
| 143 | |
| 144 | tx-pins { |
| 145 | pins = "gpio22"; |
| 146 | function = "qup1_se2"; |
| 147 | bias-disable; |
| 148 | }; |
| 149 | }; |
| 150 | }; |
| 151 | ... |