dts/upstream/Bindings/net/dsa/mscc,ocelot.yaml

# SPDX-License-Identifier: (GPL-2.0 OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/mscc,ocelot.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip Ocelot Switch Family

maintainers:
  - Vladimir Oltean <vladimir.oltean@nxp.com>
  - Claudiu Manoil <claudiu.manoil@nxp.com>
  - Alexandre Belloni <alexandre.belloni@bootlin.com>
  - UNGLinuxDriver@microchip.com

description: |
  There are multiple switches which are either part of the Ocelot-1 family, or
  derivatives of this architecture. These switches can be found embedded in
  various SoCs and accessed using MMIO, or as discrete chips and accessed over
  SPI or PCIe. The present DSA binding shall be used when the host controlling
  them performs packet I/O primarily through an Ethernet port of the switch
  (which is attached to an Ethernet port of the host), rather than through
  Frame DMA or register-based I/O.

  VSC9953 (Seville):

    This is found in the NXP T1040, where it is a memory-mapped platform
    device.

    The following PHY interface types are supported:

      - phy-mode = "internal": on ports 8 and 9
      - phy-mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
      - phy-mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
      - phy-mode = "1000base-x": on ports 0, 1, 2, 3, 4, 5, 6, 7

  VSC9959 (Felix):

    This is found in the NXP LS1028A. It is a PCI device, part of the larger
    enetc root complex. As a result, the ethernet-switch node is a sub-node of
    the PCIe root complex node and its "reg" property conforms to the parent
    node bindings, describing it as PF 5 of device 0, bus 0.

    If any external switch port is enabled, the enetc PF2 (enetc_port2) should
    be enabled as well. This is because the internal MDIO bus (exposed through
    EA BAR 0) used to access the MAC PCS registers truly belongs to the enetc
    port 2 and not to Felix.

    The following PHY interface types are supported:

      - phy-mode = "internal": on ports 4 and 5
      - phy-mode = "sgmii": on ports 0, 1, 2, 3
      - phy-mode = "qsgmii": on ports 0, 1, 2, 3
      - phy-mode = "usxgmii": on ports 0, 1, 2, 3
      - phy-mode = "1000base-x": on ports 0, 1, 2, 3
      - phy-mode = "2500base-x": on ports 0, 1, 2, 3

properties:
  compatible:
    enum:
      - mscc,vsc9953-switch
      - pci1957,eef0

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

    description:
      Used to signal availability of PTP TX timestamps, and state changes of
      the MAC merge layer of ports that support Frame Preemption.

  little-endian: true
  big-endian: true

required:
  - compatible
  - reg

allOf:
  - $ref: dsa.yaml#/$defs/ethernet-ports
  - if:
      properties:
        compatible:
          const: pci1957,eef0
    then:
      required:
        - interrupts

unevaluatedProperties: false

examples:
  # Felix VSC9959 (NXP LS1028A)
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pcie { /* Integrated Endpoint Root Complex */
        #address-cells = <3>;
        #size-cells = <2>;

        ethernet-switch@0,5 {
            compatible = "pci1957,eef0";
            reg = <0x000500 0 0 0 0>;
            interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy0>;
                    managed = "in-band-status";
                };

                port@1 {
                    reg = <1>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy1>;
                    managed = "in-band-status";
                };

                port@2 {
                    reg = <2>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy2>;
                    managed = "in-band-status";
                };

                port@3 {
                    reg = <3>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy3>;
                    managed = "in-band-status";
                };

                port@4 {
                    reg = <4>;
                    ethernet = <&enetc_port2>;
                    phy-mode = "internal";

                    fixed-link {
                        speed = <2500>;
                        full-duplex;
                        pause;
                    };
                };

                port@5 {
                    reg = <5>;
                    ethernet = <&enetc_port3>;
                    phy-mode = "internal";

                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                        pause;
                    };
                };
            };
        };
    };
  # Seville VSC9953 (NXP T1040)
  - |
    soc {
        #address-cells = <1>;
        #size-cells = <1>;

        ethernet-switch@800000 {
            compatible = "mscc,vsc9953-switch";
            reg = <0x800000 0x290000>;
            little-endian;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy0>;
                    managed = "in-band-status";
                };

                port@1 {
                    reg = <1>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy1>;
                    managed = "in-band-status";
                };

                port@2 {
                    reg = <2>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy2>;
                    managed = "in-band-status";
                };

                port@3 {
                    reg = <3>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy3>;
                    managed = "in-band-status";
                };

                port@4 {
                    reg = <4>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy4>;
                    managed = "in-band-status";
                };

                port@5 {
                    reg = <5>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy5>;
                    managed = "in-band-status";
                };

                port@6 {
                    reg = <6>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy6>;
                    managed = "in-band-status";
                };

                port@7 {
                    reg = <7>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy7>;
                    managed = "in-band-status";
                };

                port@8 {
                    reg = <8>;
                    phy-mode = "internal";
                    ethernet = <&enet0>;

                    fixed-link {
                        speed = <2500>;
                        full-duplex;
                        pause;
                    };
                };

                port@9 {
                    reg = <9>;
                    phy-mode = "internal";
                    ethernet = <&enet1>;

                    fixed-link {
                        speed = <2500>;
                        full-duplex;
                        pause;
                    };
                };
            };
        };
    };