dts/upstream/Bindings/media/nxp,imx-mipi-csi2.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver

maintainers:
  - Rui Miguel Silva <rmfrfs@gmail.com>
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description: |-
  The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
  receiver IP core named CSIS. The IP core originates from Samsung, and may be
  compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
  3.3, and i.MX8 SoCs use CSIS version 3.6.3.

  While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
  completely wrapped by the CSIS and doesn't expose a control interface of its
  own. This binding thus covers both IP cores.

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx7-mipi-csi2
          - fsl,imx8mm-mipi-csi2
      - items:
          - enum:
              - fsl,imx8mp-mipi-csi2
          - const: fsl,imx8mm-mipi-csi2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3
    items:
      - description: The peripheral clock (a.k.a. APB clock)
      - description: The external clock (optionally used as the pixel clock)
      - description: The MIPI D-PHY clock
      - description: The AXI clock

  clock-names:
    minItems: 3
    items:
      - const: pclk
      - const: wrap
      - const: phy
      - const: axi

  power-domains:
    maxItems: 1

  phy-supply:
    description: The MIPI D-PHY digital power supply

  resets:
    items:
      - description: MIPI D-PHY slave reset

  clock-frequency:
    description: The desired external clock ("wrap") frequency, in Hz
    default: 166000000

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port node, single endpoint describing the CSI-2 transmitter.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                description:
                  Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines.
                minItems: 1
                items:
                  - const: 1
                  - const: 2
                  - const: 3
                  - const: 4

            required:
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Output port node

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains
  - ports

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx7-mipi-csi2
    then:
      required:
        - phy-supply
        - resets
    else:
      properties:
        clocks:
          minItems: 4
        clock-names:
          minItems: 4
        phy-supply: false
        resets: false

examples:
  - |
    #include <dt-bindings/clock/imx7d-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/reset/imx7-reset.h>

    mipi-csi@30750000 {
        compatible = "fsl,imx7-mipi-csi2";
        reg = <0x30750000 0x10000>;
        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clks IMX7D_IPG_ROOT_CLK>,
                 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
                 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
        clock-names = "pclk", "wrap", "phy";
        clock-frequency = <166000000>;

        power-domains = <&pgc_mipi_phy>;
        phy-supply = <&reg_1p0d>;
        resets = <&src IMX7_RESET_MIPI_PHY_MRST>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                mipi_from_sensor: endpoint {
                    remote-endpoint = <&ov2680_to_mipi>;
                    data-lanes = <1>;
                };
            };

            port@1 {
                reg = <1>;

                mipi_vc0_to_csi_mux: endpoint {
                    remote-endpoint = <&csi_mux_from_mipi_vc0>;
                };
            };
        };
    };

  - |
    #include <dt-bindings/clock/imx8mm-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    mipi-csi@32e30000 {
        compatible = "fsl,imx8mm-mipi-csi2";
        reg = <0x32e30000 0x1000>;
        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
        clock-frequency = <333000000>;
        clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
                 <&clk IMX8MM_CLK_CSI1_ROOT>,
                 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
                 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
        clock-names = "pclk", "wrap", "phy", "axi";
        power-domains = <&mipi_pd>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                imx8mm_mipi_csi_in: endpoint {
                    remote-endpoint = <&imx477_out>;
                    data-lanes = <1 2 3 4>;
                };
            };

            port@1 {
                reg = <1>;

                imx8mm_mipi_csi_out: endpoint {
                    remote-endpoint = <&csi_in>;
                };
            };
        };
    };

...