| Tom Rini | 6bb92fc | 2024-05-20 09:54:58 -0600 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: StarFive External Interrupt Controller |
| 8 | |
| 9 | description: |
| 10 | StarFive SoC JH8100 contain a external interrupt controller. It can be used |
| 11 | to handle high-level input interrupt signals. It also send the output |
| 12 | interrupt signal to RISC-V PLIC. |
| 13 | |
| 14 | maintainers: |
| 15 | - Changhuang Liang <changhuang.liang@starfivetech.com> |
| 16 | |
| 17 | properties: |
| 18 | compatible: |
| 19 | const: starfive,jh8100-intc |
| 20 | |
| 21 | reg: |
| 22 | maxItems: 1 |
| 23 | |
| 24 | clocks: |
| 25 | description: APB clock for the interrupt controller |
| 26 | maxItems: 1 |
| 27 | |
| 28 | resets: |
| 29 | description: APB reset for the interrupt controller |
| 30 | maxItems: 1 |
| 31 | |
| 32 | interrupts: |
| 33 | maxItems: 1 |
| 34 | |
| 35 | interrupt-controller: true |
| 36 | |
| 37 | "#interrupt-cells": |
| 38 | const: 1 |
| 39 | |
| 40 | required: |
| 41 | - compatible |
| 42 | - reg |
| 43 | - clocks |
| 44 | - resets |
| 45 | - interrupts |
| 46 | - interrupt-controller |
| 47 | - "#interrupt-cells" |
| 48 | |
| 49 | additionalProperties: false |
| 50 | |
| 51 | examples: |
| 52 | - | |
| 53 | interrupt-controller@12260000 { |
| 54 | compatible = "starfive,jh8100-intc"; |
| 55 | reg = <0x12260000 0x10000>; |
| 56 | clocks = <&syscrg_ne 76>; |
| 57 | resets = <&syscrg_ne 13>; |
| 58 | interrupts = <45>; |
| 59 | interrupt-controller; |
| 60 | #interrupt-cells = <1>; |
| 61 | }; |