| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: MTMIPS SoCs System Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Sergio Paracuellos <sergio.paracuellos@gmail.com> |
| 11 | |
| 12 | description: | |
| 13 | MediaTek MIPS and Ralink SoCs provides a system controller to allow |
| 14 | to access to system control registers. These registers include clock |
| 15 | and reset related ones so this node is both clock and reset provider |
| 16 | for the rest of the world. |
| 17 | |
| 18 | These SoCs have an XTAL from where the cpu clock is |
| 19 | provided as well as derived clocks for the bus and the peripherals. |
| 20 | |
| 21 | properties: |
| 22 | compatible: |
| 23 | items: |
| 24 | - enum: |
| 25 | - ralink,mt7620-sysc |
| 26 | - ralink,mt7628-sysc |
| 27 | - ralink,mt7688-sysc |
| 28 | - ralink,rt2880-sysc |
| 29 | - ralink,rt3050-sysc |
| 30 | - ralink,rt3052-sysc |
| 31 | - ralink,rt3352-sysc |
| 32 | - ralink,rt3883-sysc |
| 33 | - ralink,rt5350-sysc |
| 34 | - const: syscon |
| 35 | |
| 36 | reg: |
| 37 | maxItems: 1 |
| 38 | |
| 39 | '#clock-cells': |
| 40 | description: |
| 41 | The first cell indicates the clock number. |
| 42 | const: 1 |
| 43 | |
| 44 | '#reset-cells': |
| 45 | description: |
| 46 | The first cell indicates the reset bit within the register. |
| 47 | const: 1 |
| 48 | |
| 49 | required: |
| 50 | - compatible |
| 51 | - reg |
| 52 | - '#clock-cells' |
| 53 | - '#reset-cells' |
| 54 | |
| 55 | additionalProperties: false |
| 56 | |
| 57 | examples: |
| 58 | - | |
| 59 | syscon@0 { |
| 60 | compatible = "ralink,rt5350-sysc", "syscon"; |
| 61 | reg = <0x0 0x100>; |
| 62 | #clock-cells = <1>; |
| 63 | #reset-cells = <1>; |
| 64 | }; |