| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Synopsys DWC AHCI SATA controller properties |
| 8 | |
| 9 | maintainers: |
| 10 | - Serge Semin <fancer.lancer@gmail.com> |
| 11 | |
| 12 | description: |
| 13 | This document defines device tree schema for the generic Synopsys DWC |
| 14 | AHCI controller properties. |
| 15 | |
| 16 | select: false |
| 17 | |
| 18 | allOf: |
| 19 | - $ref: ahci-common.yaml# |
| 20 | |
| 21 | properties: |
| 22 | reg: |
| 23 | maxItems: 1 |
| 24 | |
| 25 | interrupts: |
| 26 | maxItems: 1 |
| 27 | |
| 28 | clocks: |
| 29 | description: |
| 30 | Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock, |
| 31 | PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx) |
| 32 | clock, etc. |
| 33 | minItems: 1 |
| 34 | maxItems: 6 |
| 35 | |
| 36 | clock-names: |
| 37 | minItems: 1 |
| 38 | maxItems: 6 |
| 39 | items: |
| 40 | oneOf: |
| 41 | - description: Application APB/AHB/AXI BIU clock |
| 42 | enum: |
| 43 | - pclk |
| 44 | - aclk |
| 45 | - hclk |
| 46 | - sata |
| 47 | - description: Power Module keep-alive clock |
| 48 | const: pmalive |
| 49 | - description: RxOOB detection clock |
| 50 | const: rxoob |
| 51 | - description: PHY Transmit Clock |
| 52 | const: asic |
| 53 | - description: PHY Receive Clock |
| 54 | const: rbc |
| 55 | - description: SATA Ports reference clock |
| 56 | const: ref |
| 57 | |
| 58 | resets: |
| 59 | description: |
| 60 | At least basic application and reference clock domains resets are |
| 61 | normally supported by the DWC AHCI SATA controller. |
| 62 | minItems: 1 |
| 63 | maxItems: 4 |
| 64 | |
| 65 | reset-names: |
| 66 | minItems: 1 |
| 67 | maxItems: 4 |
| 68 | items: |
| 69 | oneOf: |
| 70 | - description: Application AHB/AXI BIU clock domain reset control |
| 71 | enum: |
| 72 | - arst |
| 73 | - hrst |
| 74 | - description: Power Module keep-alive clock domain reset control |
| 75 | const: pmalive |
| 76 | - description: RxOOB detection clock domain reset control |
| 77 | const: rxoob |
| 78 | - description: Reference clock domain reset control |
| 79 | const: ref |
| 80 | |
| 81 | patternProperties: |
| 82 | "^sata-port@[0-9a-e]$": |
| 83 | $ref: '#/$defs/dwc-ahci-port' |
| 84 | |
| 85 | additionalProperties: true |
| 86 | |
| 87 | $defs: |
| 88 | dwc-ahci-port: |
| 89 | $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port |
| 90 | |
| 91 | properties: |
| 92 | reg: |
| 93 | minimum: 0 |
| 94 | maximum: 7 |
| 95 | |
| 96 | snps,tx-ts-max: |
| 97 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 98 | description: Maximal size of Tx DMA transactions in FIFO words |
| 99 | enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ] |
| 100 | |
| 101 | snps,rx-ts-max: |
| 102 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 103 | description: Maximal size of Rx DMA transactions in FIFO words |
| 104 | enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ] |
| 105 | |
| 106 | ... |