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git01.mediatek.com / filogic / uboot / 6405a159ed386bdd915889dff52ff9d300326887 / . / board / ids8247 / ids8247.c
blob: 7b9a83d0f954b195830391a02977ee2d3f78cecd [file] [log] [blame]
wdenka7316b02005-05-12 22:48:09 +0000[diff] [blame]1/*
2 * (C) Copyright 2005
3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ioports.h>
26#include <mpc8260.h>
27
Wolfgang Denk6405a152006-03-31 18:32:53 +0200[diff] [blame^]28DECLARE_GLOBAL_DATA_PTR;
29
wdenka7316b02005-05-12 22:48:09 +0000[diff] [blame]30/*
31 * I/O Port configuration table
32 *
33 * if conf is 1, then that port pin will be configured at boot time
34 * according to the five values podr/pdir/ppar/psor/pdat for that entry
35 */
36
37const iop_conf_t iop_conf_tab[4][32] = {
38
39 /* Port A configuration */
40 { /* conf ppar psor pdir podr pdat */
41 /* PA31 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 COL */
42 /* PA30 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
43 /* PA29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
44 /* PA28 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
45 /* PA27 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
46 /* PA26 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
47 /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
48#if defined(CONFIG_SOFT_I2C)
49 /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
50 /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */
51#else /* normal I/O port pins */
52 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
53 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
54#endif
55 /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */
56 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
57 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
58 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
59 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
60 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
61 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
62 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
63 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
64 /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */
65 /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */
66 /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */
67 /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */
68 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
69 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
70 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
71 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
72 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
73 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
74 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
75 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
76 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
77 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
78 },
79
80 /* Port B configuration */
81 { /* conf ppar psor pdir podr pdat */
82 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
83 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
84 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
85 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
86 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
87 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
88 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
89 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
90 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
91 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
92 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
93 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
94 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
95 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
96 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
97 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
98 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
99 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
100 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
101 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
102 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
103 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
104 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
105 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
106 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
107 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
108 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
109 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
110 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
111 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
112 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
113 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
114 },
115
116 /* Port C */
117 { /* conf ppar psor pdir podr pdat */
118 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
119 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
120 /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */
121 /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */
122 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
123 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
124 /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */
125 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
126 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
127 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
128 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
129 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
130 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
131 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
132 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
133 /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
134 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
135 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
136 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
137 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
138 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
139 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
140 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
141 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
142 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
143 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
144 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
145 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
146 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
147 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
148 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
149 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
150 },
151
152 /* Port D */
153 { /* conf ppar psor pdir podr pdat */
154 /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
155 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
156 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
157 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
158 /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
159 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
160 /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */
161 /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */
162 /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */
163 /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */
164 /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */
165 /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */
166 /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */
167 /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */
168 /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */
169 /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */
170#if defined(CONFIG_HARD_I2C)
171 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */
172 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */
173#else /* normal I/O port pins */
174 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */
175 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */
176#endif
177 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
178 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
179 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
180 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
181 /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
182 /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
183 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* MII_MDIO */
184 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
185 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
186 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
187 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
188 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
189 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
190 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
191 }
192};
193
194/* ------------------------------------------------------------------------- */
195
196/* Check Board Identity:
197 */
198int checkboard (void)
199{
200 puts ("Board: IDS 8247\n");
201 return 0;
202}
203
204/* ------------------------------------------------------------------------- */
205
206/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
207 *
208 * This routine performs standard 8260 initialization sequence
209 * and calculates the available memory size. It may be called
210 * several times to try different SDRAM configurations on both
211 * 60x and local buses.
212 */
213static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
214 ulong orx, volatile uchar * base)
215{
216 volatile uchar c = 0xff;
217 volatile uint *sdmr_ptr;
218 volatile uint *orx_ptr;
219 ulong maxsize, size;
220 int i;
221
222 /* We must be able to test a location outsize the maximum legal size
223 * to find out THAT we are outside; but this address still has to be
224 * mapped by the controller. That means, that the initial mapping has
225 * to be (at least) twice as large as the maximum expected size.
226 */
227 maxsize = (1 + (~orx | 0x7fff)) / 2;
228
229 sdmr_ptr = &memctl->memc_psdmr;
230 orx_ptr = &memctl->memc_or2;
231
232 *orx_ptr = orx;
233
234 /*
235 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
236 *
237 * "At system reset, initialization software must set up the
238 * programmable parameters in the memory controller banks registers
239 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
240 * system software should execute the following initialization sequence
241 * for each SDRAM device.
242 *
243 * 1. Issue a PRECHARGE-ALL-BANKS command
244 * 2. Issue eight CBR REFRESH commands
245 * 3. Issue a MODE-SET command to initialize the mode register
246 *
247 * The initial commands are executed by setting P/LSDMR[OP] and
248 * accessing the SDRAM with a single-byte transaction."
249 *
250 * The appropriate BRx/ORx registers have already been set when we
251 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
252 */
253
254 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
255 *base = c;
256
257 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
258 for (i = 0; i < 8; i++)
259 *base = c;
260
261 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
262 *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
263
264 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
265 *base = c;
266
267 size = get_ram_size((long *)base, maxsize);
268 *orx_ptr = orx | ~(size - 1);
269
270 return (size);
271}
272
273long int initdram (int board_type)
274{
275 volatile immap_t *immap = (immap_t *) CFG_IMMR;
276 volatile memctl8260_t *memctl = &immap->im_memctl;
277
278 long psize, lsize;
279
280 psize = 16 * 1024 * 1024;
281 lsize = 0;
282
283 memctl->memc_psrt = CFG_PSRT;
284 memctl->memc_mptpr = CFG_MPTPR;
285
286#ifndef CFG_RAMBOOT
287 /* 60x SDRAM setup:
288 */
289 psize = try_init (memctl, CFG_PSDMR, CFG_OR2,
290 (uchar *) CFG_SDRAM_BASE);
291#endif /* CFG_RAMBOOT */
292
293 icache_enable ();
294
295 return (psize);
296}
297
298int misc_init_r (void)
299{
wdenka7316b02005-05-12 22:48:09 +0000[diff] [blame]300 gd->bd->bi_flashstart = 0xff800000;
301}
302
303#if (CONFIG_COMMANDS & CFG_CMD_NAND)
304extern ulong
305nand_probe (ulong physadr);
306
307void
308nand_init (void)
309{
310 ulong totlen = 0;
311
312 debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
313 totlen += nand_probe (CFG_NAND0_BASE);
314
315 printf ("%4lu MB\n", totlen >>20);
316}
317
318#endif /* CFG_CMD_NAND */