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Haiying Wangb834f922008-10-03 12:37:10 -04001
2Table of interleaving modes supported in cpu/8xxx/ddr/
3======================================================
4 +-------------+---------------------------------------------------------+
5 | | Rank Interleaving |
6 | +--------+-----------+-----------+------------+-----------+
7 |Memory | | | | 2x2 | 4x1 |
8 |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
9 |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
10 +-------------+--------+-----------+-----------+------------+-----------+
11 |None | Yes | Yes | Yes | Yes | Yes |
12 +-------------+--------+-----------+-----------+------------+-----------+
13 |Cacheline | Yes | Yes | No | No, Only(*)| Yes |
14 | |CS0 Only| | | {CS0+CS1} | |
15 +-------------+--------+-----------+-----------+------------+-----------+
16 |Page | Yes | Yes | No | No, Only(*)| Yes |
17 | |CS0 Only| | | {CS0+CS1} | |
18 +-------------+--------+-----------+-----------+------------+-----------+
19 |Bank | Yes | Yes | No | No, Only(*)| Yes |
20 | |CS0 Only| | | {CS0+CS1} | |
21 +-------------+--------+-----------+-----------+------------+-----------+
22 |Superbank | No | Yes | No | No, Only(*)| Yes |
23 | | | | | {CS0+CS1} | |
24 +-------------+--------+-----------+-----------+------------+-----------+
25 (*) Although the hardware can be configured with memory controller
26 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
27 from each controller. {CS2+CS3} on each controller are only rank
28 interleaved on that controller.
29
30The ways to configure the ddr interleaving mode
31==============================================
321. In board header file(e.g.MPC8572DS.h), add default interleaving setting
33 under "CONFIG_EXTRA_ENV_SETTINGS", like:
34 #define CONFIG_EXTRA_ENV_SETTINGS \
Kumar Gala64042092010-07-14 10:04:21 -050035 "hwconfig=fsl_ddr:ctlr_intlv=bank" \
Haiying Wangb834f922008-10-03 12:37:10 -040036 ......
37
382. Run u-boot "setenv" command to configure the memory interleaving mode.
39 Either numerical or string value is accepted.
40
41 # disable memory controller interleaving
Kumar Gala64042092010-07-14 10:04:21 -050042 setenv hwconfig "fsl_ddr:ctlr_intlv=null"
Haiying Wangb834f922008-10-03 12:37:10 -040043
44 # cacheline interleaving
Kumar Gala64042092010-07-14 10:04:21 -050045 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
Haiying Wangb834f922008-10-03 12:37:10 -040046
47 # page interleaving
Kumar Gala64042092010-07-14 10:04:21 -050048 setenv hwconfig "fsl_ddr:ctlr_intlv=page"
Haiying Wangb834f922008-10-03 12:37:10 -040049
50 # bank interleaving
Kumar Gala64042092010-07-14 10:04:21 -050051 setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
Haiying Wangb834f922008-10-03 12:37:10 -040052
53 # superbank
Kumar Gala64042092010-07-14 10:04:21 -050054 setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
Haiying Wangb834f922008-10-03 12:37:10 -040055
56 # disable bank (chip-select) interleaving
Kumar Gala64042092010-07-14 10:04:21 -050057 setenv hwconfig "fsl_ddr:bank_intlv=null"
Haiying Wangb834f922008-10-03 12:37:10 -040058
59 # bank(chip-select) interleaving cs0+cs1
Kumar Gala64042092010-07-14 10:04:21 -050060 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
Haiying Wangb834f922008-10-03 12:37:10 -040061
62 # bank(chip-select) interleaving cs2+cs3
Kumar Gala64042092010-07-14 10:04:21 -050063 setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
Haiying Wangb834f922008-10-03 12:37:10 -040064
65 # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
Kumar Gala64042092010-07-14 10:04:21 -050066 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
Haiying Wangb834f922008-10-03 12:37:10 -040067
68 # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
Kumar Gala64042092010-07-14 10:04:21 -050069 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
70
71 The above memory controller interleaving and bank interleaving can be mixed. The syntax is
72 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1"