blob: 301b07d5b480cb20205bf919b3b0c99389266c80 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Agner41f75bb2016-07-20 21:27:49 -07002/*
Stefan Agnercbd59fe2018-08-06 09:19:19 +02003 * Copyright (C) 2016-2018 Toradex AG
Stefan Agner41f75bb2016-07-20 21:27:49 -07004 */
5
Simon Glass8e16b1e2019-12-28 10:45:05 -07006#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -07007#include <cpu_func.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -07008#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -06009#include <net.h>
Stefan Agner41f75bb2016-07-20 21:27:49 -070010#include <asm/arch/clock.h>
11#include <asm/arch/crm_regs.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/mx7-pins.h>
14#include <asm/arch/sys_proto.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060015#include <asm/global_data.h>
Stefan Agner41f75bb2016-07-20 21:27:49 -070016#include <asm/gpio.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020017#include <asm/mach-imx/iomux-v3.h>
Stefan Agner41f75bb2016-07-20 21:27:49 -070018#include <asm/io.h>
19#include <common.h>
20#include <dm.h>
21#include <dm/platform_data/serial_mxc.h>
Stefan Agner6a667482017-03-09 17:17:54 -080022#include <fdt_support.h>
Yangbo Lu73340382019-06-21 11:42:28 +080023#include <fsl_esdhc_imx.h>
Stefan Agner6a667482017-03-09 17:17:54 -080024#include <jffs2/load_kernel.h>
Simon Glassdbd79542020-05-10 11:40:11 -060025#include <linux/delay.h>
Stefan Agner41f75bb2016-07-20 21:27:49 -070026#include <linux/sizes.h>
27#include <mmc.h>
28#include <miiphy.h>
Stefan Agner6a667482017-03-09 17:17:54 -080029#include <mtd_node.h>
Stefan Agner41f75bb2016-07-20 21:27:49 -070030#include <netdev.h>
Stefan Agnere65377a2016-10-05 15:27:11 -070031#include <power/pmic.h>
32#include <power/rn5t567_pmic.h>
Stefan Agner443166e2017-03-09 17:17:52 -080033#include <usb.h>
Stefan Agner41f75bb2016-07-20 21:27:49 -070034#include <usb/ehci-ci.h>
Stefan Agner98ffd0f2016-11-30 13:41:53 -080035#include "../common/tdx-common.h"
Stefan Agner41f75bb2016-07-20 21:27:49 -070036
37DECLARE_GLOBAL_DATA_PTR;
38
39#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
40 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
41
Stefan Agner41f75bb2016-07-20 21:27:49 -070042#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
43#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
44
45#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
46
Stefan Agner41f75bb2016-07-20 21:27:49 -070047#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
48 PAD_CTL_DSE_3P3V_49OHM)
49
50#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
51
52#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
53
Stefan Agner443166e2017-03-09 17:17:52 -080054#define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
55
Stefan Agner41f75bb2016-07-20 21:27:49 -070056int dram_init(void)
57{
Fabio Estevamf8774732018-09-19 13:01:56 +020058 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
Stefan Agner41f75bb2016-07-20 21:27:49 -070059
60 return 0;
61}
62
63static iomux_v3_cfg_t const uart1_pads[] = {
64 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
65 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
66 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
67 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
68};
69
Stefan Agner443166e2017-03-09 17:17:52 -080070#ifdef CONFIG_USB_EHCI_MX7
71static iomux_v3_cfg_t const usb_cdet_pads[] = {
72 MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
73};
74#endif
Stefan Agner41f75bb2016-07-20 21:27:49 -070075
Stefan Agnercbd59fe2018-08-06 09:19:19 +020076#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
Stefan Agner41f75bb2016-07-20 21:27:49 -070077static iomux_v3_cfg_t const gpmi_pads[] = {
78 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
79 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
80 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
81 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
82 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
83 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
84 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
85 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
86 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
87 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
88 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
89 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
90 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
91 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
92 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
93};
94
95static void setup_gpmi_nand(void)
96{
97 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
98
99 /* NAND_USDHC_BUS_CLK is set in rom */
100 set_clk_nand();
101}
102#endif
103
Igor Opaniuk0d649c92020-07-15 13:31:05 +0300104#ifdef CONFIG_DM_VIDEO
Stefan Agner41f75bb2016-07-20 21:27:49 -0700105static iomux_v3_cfg_t const backlight_pads[] = {
106 /* Backlight On */
107 MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
108 /* Backlight PWM<A> (multiplexed pin) */
109 MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
110 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
111};
112
113#define GPIO_BL_ON IMX_GPIO_NR(5, 1)
114#define GPIO_PWM_A IMX_GPIO_NR(1, 8)
115
116static int setup_lcd(void)
117{
Stefan Agner41f75bb2016-07-20 21:27:49 -0700118 imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
119
120 /* Set BL_ON */
121 gpio_request(GPIO_BL_ON, "BL_ON");
122 gpio_direction_output(GPIO_BL_ON, 1);
123
124 /* Set PWM<A> to full brightness (assuming inversed polarity) */
125 gpio_request(GPIO_PWM_A, "PWM<A>");
126 gpio_direction_output(GPIO_PWM_A, 0);
127
128 return 0;
129}
130#endif
131
Gerard Salvatella108d7392018-11-19 15:54:10 +0100132/*
133 * Backlight off before OS handover
134 */
135void board_preboot_os(void)
136{
Igor Opaniukefe398f2020-09-14 11:01:07 +0300137#ifdef CONFIG_DM_VIDEO
Gerard Salvatella108d7392018-11-19 15:54:10 +0100138 gpio_direction_output(GPIO_PWM_A, 1);
139 gpio_direction_output(GPIO_BL_ON, 0);
Igor Opaniukefe398f2020-09-14 11:01:07 +0300140#endif
Gerard Salvatella108d7392018-11-19 15:54:10 +0100141}
142
Stefan Agner41f75bb2016-07-20 21:27:49 -0700143static void setup_iomux_uart(void)
144{
145 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
146}
147
Stefan Agner41f75bb2016-07-20 21:27:49 -0700148#ifdef CONFIG_FEC_MXC
Stefan Agner41f75bb2016-07-20 21:27:49 -0700149static int setup_fec(void)
150{
151 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
152 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
153
154#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
155 /*
156 * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
157 * and output it on the pin
158 */
159 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
160 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
161 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
162#else
163 /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
164 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
165 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
166 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
167#endif
168
Eric Nelsoneadd7322017-08-31 08:34:23 -0700169 return set_clk_enet(ENET_50MHZ);
Stefan Agner41f75bb2016-07-20 21:27:49 -0700170}
171
Stefan Agner41f75bb2016-07-20 21:27:49 -0700172#endif
173
174int board_early_init_f(void)
175{
176 setup_iomux_uart();
177
Stefan Agner41f75bb2016-07-20 21:27:49 -0700178 return 0;
179}
180
181int board_init(void)
182{
183 /* address of boot parameters */
184 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
185
186#ifdef CONFIG_FEC_MXC
187 setup_fec();
188#endif
189
Stefan Agnercbd59fe2018-08-06 09:19:19 +0200190#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
Stefan Agner41f75bb2016-07-20 21:27:49 -0700191 setup_gpmi_nand();
192#endif
193
Stefan Agner443166e2017-03-09 17:17:52 -0800194#ifdef CONFIG_USB_EHCI_MX7
195 imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
196 gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
197#endif
198
Stefan Agner41f75bb2016-07-20 21:27:49 -0700199 return 0;
200}
201
Stefan Agnere65377a2016-10-05 15:27:11 -0700202#ifdef CONFIG_DM_PMIC
203int power_init_board(void)
204{
205 struct udevice *dev;
206 int reg, ver;
207 int ret;
208
209
Igor Opaniuka4e8f5f2019-07-22 12:05:06 +0300210 ret = pmic_get("rn5t567@33", &dev);
Stefan Agnere65377a2016-10-05 15:27:11 -0700211 if (ret)
212 return ret;
213 ver = pmic_reg_read(dev, RN5T567_LSIVER);
214 reg = pmic_reg_read(dev, RN5T567_OTPVER);
215
216 printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
217
218 /* set judge and press timer of N_OE to minimal values */
219 pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
220
Stefan Agner0f2c5ad2017-03-09 17:17:53 -0800221 /* configure sleep slot for 3.3V Ethernet */
222 reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
223 reg = (reg & 0xf0) | reg >> 4;
224 pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
225
226 /* disable DCDC2 discharge to avoid backfeeding through VFB2 */
227 pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
228
229 /* configure sleep slot for ARM rail */
230 reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
231 reg = (reg & 0xf0) | reg >> 4;
232 pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
233
234 /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
235 pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
236
Stefan Agnere65377a2016-10-05 15:27:11 -0700237 return 0;
238}
239
Harald Seiler6f14d5f2020-12-15 16:47:52 +0100240void reset_cpu(void)
Stefan Agnere65377a2016-10-05 15:27:11 -0700241{
242 struct udevice *dev;
243
Igor Opaniuka4e8f5f2019-07-22 12:05:06 +0300244 pmic_get("rn5t567@33", &dev);
Stefan Agnere65377a2016-10-05 15:27:11 -0700245
246 /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
247 pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
248 pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
249
250 /*
251 * Re-power factor detection on PMIC side is not instant. 1ms
252 * proved to be enough time until reset takes effect.
253 */
254 mdelay(1);
255}
256#endif
257
Stefan Agner41f75bb2016-07-20 21:27:49 -0700258int checkboard(void)
259{
260 printf("Model: Toradex Colibri iMX7%c\n",
261 is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
262
263 return 0;
264}
265
Stefan Agner98ffd0f2016-11-30 13:41:53 -0800266#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900267int ft_board_setup(void *blob, struct bd_info *bd)
Stefan Agner98ffd0f2016-11-30 13:41:53 -0800268{
Igor Opaniukcbee9452019-12-03 14:04:47 +0200269#if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
270 int up;
271
272 up = arch_auxiliary_core_check_up(0);
273 if (up) {
274 int ret;
275 int areas = 1;
276 u64 start[2], size[2];
277
278 /*
279 * Reserve 1MB of memory for M4 (1MiB is also the minimum
280 * alignment for Linux due to MMU section size restrictions).
281 */
282 start[0] = gd->bd->bi_dram[0].start;
283 size[0] = SZ_256M - SZ_1M;
284
285 /* If needed, create a second entry for memory beyond 256M */
286 if (gd->bd->bi_dram[0].size > SZ_256M) {
287 start[1] = gd->bd->bi_dram[0].start + SZ_256M;
288 size[1] = gd->bd->bi_dram[0].size - SZ_256M;
289 areas = 2;
290 }
291
292 ret = fdt_set_usable_memory(blob, start, size, areas);
293 if (ret) {
294 eprintf("Cannot set usable memory\n");
295 return ret;
296 }
297 } else {
298 int off;
299
300 off = fdt_node_offset_by_compatible(blob, -1,
301 "fsl,imx7d-rpmsg");
302 if (off > 0)
303 fdt_status_disabled(blob, off);
304 }
305#endif
Stefan Agner6a667482017-03-09 17:17:54 -0800306#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
Masahiro Yamada20ead6f2018-07-19 16:28:23 +0900307 static const struct node_info nodes[] = {
Stefan Agner6a667482017-03-09 17:17:54 -0800308 { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
Stefan Agnerb2f4ea92018-06-26 11:10:51 +0200309 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
Stefan Agner6a667482017-03-09 17:17:54 -0800310 };
311
312 /* Update partition nodes using info from mtdparts env var */
313 puts(" Updating MTD partitions...\n");
314 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
315#endif
316
Stefan Agner98ffd0f2016-11-30 13:41:53 -0800317 return ft_common_board_setup(blob, bd);
318}
319#endif
320
Stefan Agner41f75bb2016-07-20 21:27:49 -0700321#ifdef CONFIG_USB_EHCI_MX7
322static iomux_v3_cfg_t const usb_otg2_pads[] = {
323 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
324};
325
326int board_ehci_hcd_init(int port)
327{
328 switch (port) {
329 case 0:
330 break;
331 case 1:
332 if (is_cpu_type(MXC_CPU_MX7S))
333 return -ENODEV;
334
335 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
336 ARRAY_SIZE(usb_otg2_pads));
337 break;
338 default:
339 return -EINVAL;
340 }
341 return 0;
342}
Stefan Agner443166e2017-03-09 17:17:52 -0800343
344int board_usb_phy_mode(int port)
345{
346 switch (port) {
347 case 0:
348 if (gpio_get_value(USB_CDET_GPIO))
349 return USB_INIT_DEVICE;
350 else
351 return USB_INIT_HOST;
352 case 1:
353 default:
354 return USB_INIT_HOST;
355 }
356}
Igor Opaniuk0d649c92020-07-15 13:31:05 +0300357
358int board_late_init(void)
359{
360#if defined(CONFIG_DM_VIDEO)
361 setup_lcd();
Igor Opaniuk0d649c92020-07-15 13:31:05 +0300362#endif
363 return 0;
364}
365
Stefan Agner41f75bb2016-07-20 21:27:49 -0700366#endif