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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Matt Waddel35c638b2010-10-07 15:48:45 -06002/*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
6 *
7 * (C) Copyright 2002
8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
9 *
10 * (C) Copyright 2003
11 * Texas Instruments, <www.ti.com>
12 * Kshitij Gupta <Kshitij@ti.com>
13 *
14 * (C) Copyright 2004
15 * ARM Ltd.
16 * Philippe Robin, <philippe.robin@arm.com>
Matt Waddel35c638b2010-10-07 15:48:45 -060017 */
18#include <common.h>
Simon Glass1ea97892020-05-10 11:40:00 -060019#include <bootstage.h>
Simon Glass370382c2019-11-14 12:57:35 -070020#include <cpu_func.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -070021#include <init.h>
John Rigby03f609b2012-07-31 08:59:31 +000022#include <malloc.h>
23#include <errno.h>
Simon Glass274e0b02020-05-10 11:39:56 -060024#include <net.h>
Matt Waddel35c638b2010-10-07 15:48:45 -060025#include <netdev.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060026#include <asm/global_data.h>
Matt Waddel35c638b2010-10-07 15:48:45 -060027#include <asm/io.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -060028#include <asm/mach-types.h>
Matt Waddel35c638b2010-10-07 15:48:45 -060029#include <asm/arch/systimer.h>
30#include <asm/arch/sysctrl.h>
31#include <asm/arch/wdt.h>
Dirk Behme89f4f0d2011-05-23 07:40:26 +000032#include "../drivers/mmc/arm_pl180_mmci.h"
Matt Waddel35c638b2010-10-07 15:48:45 -060033
Ryan Harkin0e5827f2013-04-09 02:20:31 +000034static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
Matt Waddel35c638b2010-10-07 15:48:45 -060035static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
36
37static void flash__init(void);
38static void vexpress_timer_init(void);
39DECLARE_GLOBAL_DATA_PTR;
40
41#if defined(CONFIG_SHOW_BOOT_PROGRESS)
42void show_boot_progress(int progress)
43{
44 printf("Boot reached stage %d\n", progress);
45}
46#endif
47
48static inline void delay(ulong loops)
49{
50 __asm__ volatile ("1:\n"
51 "subs %0, %1, #1\n"
52 "bne 1b" : "=r" (loops) : "0" (loops));
53}
54
55int board_init(void)
56{
57 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
58 gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
Matt Waddel35c638b2010-10-07 15:48:45 -060059
60 icache_enable();
61 flash__init();
62 vexpress_timer_init();
63
64 return 0;
65}
66
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090067int board_eth_init(struct bd_info *bis)
Matt Waddel35c638b2010-10-07 15:48:45 -060068{
69 int rc = 0;
70#ifdef CONFIG_SMC911X
71 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
72#endif
73 return rc;
74}
75
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090076int cpu_mmc_init(struct bd_info *bis)
Matt Waddelc5a6a402011-04-16 11:54:08 +000077{
78 int rc = 0;
John Rigby03f609b2012-07-31 08:59:31 +000079 (void) bis;
Matt Waddelc5a6a402011-04-16 11:54:08 +000080#ifdef CONFIG_ARM_PL180_MMCI
John Rigby03f609b2012-07-31 08:59:31 +000081 struct pl180_mmc_host *host;
Patrice Chotard2a392fe2017-10-23 10:57:30 +020082 struct mmc *mmc;
John Rigby03f609b2012-07-31 08:59:31 +000083
84 host = malloc(sizeof(struct pl180_mmc_host));
85 if (!host)
86 return -ENOMEM;
87 memset(host, 0, sizeof(*host));
88
89 strcpy(host->name, "MMC");
90 host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
91 host->pwr_init = INIT_PWR;
92 host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
93 host->voltages = VOLTAGE_WINDOW_MMC;
94 host->caps = 0;
95 host->clock_in = ARM_MCLK;
96 host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
97 host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
Patrice Chotard2a392fe2017-10-23 10:57:30 +020098 rc = arm_pl180_mmci_init(host, &mmc);
Matt Waddelc5a6a402011-04-16 11:54:08 +000099#endif
100 return rc;
101}
102
Matt Waddel35c638b2010-10-07 15:48:45 -0600103static void flash__init(void)
104{
105 /* Setup the sytem control register to allow writing to flash */
106 writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
107 &sysctrl_base->scflashctrl);
108}
109
110int dram_init(void)
111{
Matt Waddela1d3bc42010-11-02 17:25:21 -0600112 gd->ram_size =
113 get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
Matt Waddel35c638b2010-10-07 15:48:45 -0600114 return 0;
115}
116
Simon Glass2f949c32017-03-31 08:40:32 -0600117int dram_init_banksize(void)
Matt Waddel35c638b2010-10-07 15:48:45 -0600118{
119 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
Matt Waddela1d3bc42010-11-02 17:25:21 -0600120 gd->bd->bi_dram[0].size =
121 get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
Matt Waddel35c638b2010-10-07 15:48:45 -0600122 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
Matt Waddela1d3bc42010-11-02 17:25:21 -0600123 gd->bd->bi_dram[1].size =
124 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
Simon Glass2f949c32017-03-31 08:40:32 -0600125
126 return 0;
Matt Waddel35c638b2010-10-07 15:48:45 -0600127}
128
Matt Waddel35c638b2010-10-07 15:48:45 -0600129/*
130 * Start timer:
131 * Setup a 32 bit timer, running at 1KHz
132 * Versatile Express Motherboard provides 1 MHz timer
133 */
134static void vexpress_timer_init(void)
135{
136 /*
137 * Set clock frequency in system controller:
138 * VEXPRESS_REFCLK is 32KHz
139 * VEXPRESS_TIMCLK is 1MHz
140 */
141 writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
142 SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
143 readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
144
145 /*
146 * Set Timer0 to be:
147 * Enabled, free running, no interrupt, 32-bit, wrapping
148 */
149 writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
150 writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
Ryan Harkinf9f84812013-04-09 02:20:30 +0000151 writel(SYSTIMER_EN | SYSTIMER_32BIT |
152 readl(&systimer_base->timer0control),
Matt Waddel35c638b2010-10-07 15:48:45 -0600153 &systimer_base->timer0control);
Matt Waddel35c638b2010-10-07 15:48:45 -0600154}
155
Ryan Harkin0e5827f2013-04-09 02:20:31 +0000156int v2m_cfg_write(u32 devfn, u32 data)
157{
158 /* Configuration interface broken? */
159 u32 val;
160
161 devfn |= SYS_CFG_START | SYS_CFG_WRITE;
162
163 val = readl(V2M_SYS_CFGSTAT);
164 writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
165
166 writel(data, V2M_SYS_CFGDATA);
167 writel(devfn, V2M_SYS_CFGCTRL);
168
169 do {
170 val = readl(V2M_SYS_CFGSTAT);
171 } while (val == 0);
172
173 return !!(val & SYS_CFG_ERR);
174}
175
Matt Waddel35c638b2010-10-07 15:48:45 -0600176/* Use the ARM Watchdog System to cause reset */
Harald Seiler6f14d5f2020-12-15 16:47:52 +0100177void reset_cpu(void)
Matt Waddel35c638b2010-10-07 15:48:45 -0600178{
Ryan Harkin0e5827f2013-04-09 02:20:31 +0000179 if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
180 printf("Unable to reboot\n");
Matt Waddel35c638b2010-10-07 15:48:45 -0600181}
182
Matt Waddel35c638b2010-10-07 15:48:45 -0600183void lowlevel_init(void)
184{
185}
186
187ulong get_board_rev(void){
188 return readl((u32 *)SYS_ID);
189}
Liming Wang1acfeac2012-02-22 04:56:31 +0000190
Jan Kiszkaac31b5a2015-04-21 07:18:24 +0200191#ifdef CONFIG_ARMV7_NONSEC
Andre Przywara55b19aa2013-09-19 18:06:46 +0200192/* Setting the address at which secondary cores start from.
193 * Versatile Express uses one address for all cores, so ignore corenr
194 */
195void smp_set_core_boot_addr(unsigned long addr, int corenr)
196{
197 /* The SYSFLAGS register on VExpress needs to be cleared first
198 * by writing to the next address, since any writes to the address
199 * at offset 0 will only be ORed in
200 */
201 writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
202 writel(addr, CONFIG_SYSFLAGS_ADDR);
203}
204#endif