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git01.mediatek.com / filogic / uboot / 635f9244ebf8f60cbcd9ae3df1278515b934b476 / . / include / configs / theadorable.h
blob: 746bdb74e2b5fb96824e14127910ad72736000a8 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]2/*
3 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]4 */
5
6#ifndef _CONFIG_THEADORABLE_H
7#define _CONFIG_THEADORABLE_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]12
13/*
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
16 * U-Boot into it.
17 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]18
19/*
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]20 * The debugging version enables USB support via defconfig.
21 * This version should also enable all other non-production
22 * interfaces / features.
23 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]24
25/* I2C */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]26#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roese07b5e042016-04-08 15:58:29 +0200[diff] [blame]27#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]28
29/* USB/EHCI configuration */
30#define CONFIG_EHCI_IS_TDI
31#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
32
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]33/* Environment in SPI NOR flash */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]34
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]35#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
36
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]37/* Keep device tree and initrd in lower memory so the kernel can access them */
38#define CONFIG_EXTRA_ENV_SETTINGS \
39 "fdt_high=0x10000000\0" \
40 "initrd_high=0x10000000\0"
41
42/* SATA support */
43#define CONFIG_SYS_SATA_MAX_DEVICE 1
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]44#define CONFIG_LBA48
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]45
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]46/* Enable LCD and reserve 512KB from top of memory*/
47#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
48
Stefan Roesef0547582016-02-12 14:24:07 +0100[diff] [blame]49/* FPGA programming support */
Stefan Roesef0547582016-02-12 14:24:07 +0100[diff] [blame]50#define CONFIG_FPGA_STRATIX_V
51
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]52/*
Stefan Roese1a4e9802016-04-07 10:48:14 +0200[diff] [blame]53 * Bootcounter
54 */
Stefan Roese1a4e9802016-04-07 10:48:14 +0200[diff] [blame]55/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
56#define BOOTCOUNT_ADDR 0x1000
57
58/*
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]59 * mv-common.h should be defined after CMD configs since it used them
60 * to enable certain macros
61 */
62#include "mv-common.h"
63
64/*
65 * Memory layout while starting into the bin_hdr via the
66 * BootROM:
67 *
68 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
69 * 0x4000.4030 bin_hdr start address
70 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
71 * 0x4007.fffc BootROM stack top
72 *
73 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
74 * L2 cache thus cannot be used.
75 */
76
77/* SPL */
78/* Defines for SPL */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]79#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
80
81#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
82#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
83
84#ifdef CONFIG_SPL_BUILD
85#define CONFIG_SYS_MALLOC_SIMPLE
86#endif
87
88#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
89#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
90
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]91/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
92#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
93
94#endif /* _CONFIG_THEADORABLE_H */